International Journals

  1. Suwan Kim and Taewhan Kim
    Design and Utilization of Multi-skewed Multi-bit Flip-flop Cells for Timing Optimization: Design and Technology Co-optimization Approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (accepted).
  2. Kyungjoon Chang and Taewhan Kim
    Pre-route Timing Prediction and Optimization with Graph Neural Network Models
    Integration, the VLSI Journal Vol. 99, November 2024.
  3. Hyunbum Park, Kyeonghyeon Baek, Suwan Kim, Kyu-Myung Choi, and Taewhan Kim
    Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes with Consolidated Practical Applicability and Sustainability
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (accepted).
  4. Jooyeon Jeong and Taewhan Kim
    Placement Legalization for Heterogeneous Cells of Non-Integer Multiple-Heights
    Integration, the VLSI Journal March 2024.
  5. Jaehoon Ahn, Kyungjoon Chang, Kyu-Myung Choi, Taewhan Kim, and Heechun Park
    DTOC-P: Deep-learning-driven Timing Optimization using Commercial EDA Tool with Practicality Enhancement
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 43, No. 8, pp. 2493-2506, August 2024.
  6. Soomin Kim and Taewhan Kim
    Enhancing Design Qualities Utilizing Multi-bit Flip-flops: A Design and Technology Co-optimization Driven Approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 43, No. 5, pp. 1538-1551, May 2024.
  7. Kyeonghyeon Baek and Taewhan Kim
    CSyn-fp: Standard Cell Synthesis of Advanced Nodes with Simultaneous Transistor Folding and Placement
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 43, No. 2, pp. 627-640, February 2024.
  8. Eunsol Jeong, Taewhan Kim, and Heechun Park
    Eliminating Minimum Implant Area Violations with Design Quality Preservation
    IEEE Transactions on VLSI Systems Vol. 31, No. 5, pp. 611-621, May 2023.
  9. Sehyeon Chung and Taewhan Kim
    ECO Routing Based on Network Flow Method
    Integration, the VLSI Journal Vol. 86, pp. 1-8, September 2022.
  10. Jeongwoo Heo, Kwangok Jeong, Jungyun Choi, Taewhan Kim, and Kyumyung Choi
    Hardware Performance Monitoring Methodology for Circuits at Near-Threshold Computing and Advanced Technology Nodes: From Design to Post-Silicon
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 41, No. 6, pp. 1929-1942, June 2022.
  11. Jongsung Kang and Taewhan Kim
    Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks
    Journal of Computing Science and Engineering Vol. 161, No. 2, pp. 79-87, June 2022.
  12. Byungmin Ahn and Taewhan Kim
    Deeper Pruning without Accuracy Loss in Deep Neural Networks: Signed-digit Representation-based Approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 41, No. 3, pp. 656-668, March 2022.
  13. Heechun Park and Taewhan Kim
    Speeding-up Neuromorphic Computation for Neural Networks: Structure Optimization Approach
    Integration, the VLSI Journal Vol. 82, pp. 104-114, Jan. 2022.
  14. Jeongwoo Heo and Taewhan Kim
    Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
    IEEE Transactions on VLSI Systems Vol. 29, No. 7, pp. 1437-1450, July 2021.
  15. Gyounghwan Hyun and Taewhan Kim
    Allocation of Multi-Bit Retention Flip-flops for Power Gated Circuits: Algorithm – Design Unified Approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40, No. 5, pp. 892-903, May 2021.
  16. Changho Han and Taewhan Kim
    Synthesis of Representative Critical Path Circuits Considering BEOL Variations for Deep Sub-micron Circuits
    Integration, the VLSI Journal Vol. 78, pp. 1-10 May, 2021.
  17. Taehwan Kim, Heechun Park, and Taewhan Kim
    Allocation of Always-On State Retention Storage for Power Gated Circuits – Steady State Driven Approach
    IEEE Transactions on VLSI Systems Vol 29, No. 3, pp. 499-511, March 2021.
  18. Byungmin Ahn and Taewhan Kim
    Algorithm for Efficient Extraction of Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks
    Journal of Circuits, Systems, and Computers Vol. 30, No. 09, 2021.
  19. Taehwan Kim, Kwangok Jeong, Jungyun Choi, Taewhan Kim, and Kyumyung Choi
    SRAM On-chip Monitoring Methodology for High Yield and Energy Ecient Memory Operation at Near Threshold Voltage
    Integration, the VLSI Journal Vol. 74, pp. 81-92, September 2020.
  20. Jongsung Kang and Taewhan Kim
    PV-MAC: Multiply-and-Accumulate Unit Structure Exploiting Precision Variability in On-Device Convolutional Neural Networks
    Integration, the VLSI Journal Vol. 71, pp. 76-85, March 2020.
  21. Kyeongrok Jo, Seyong Ahn, Jungho Do, Taejoong Song, Taewhan Kim, and Kyumyung Choi
    Design Rule Evaluation Framework using Automatic Cell Layout Generator for Design Technology Co-Optimization
    IEEE Transactions on VLSI Systems Vol. 27, No. 8, pp. 1933-1946, August 2019.
  22. Heechun Park and Taewhan Kim
    Hybrid Asynchronous Circuit Generation Amenable to Conventional EDA Flow
    Integration, the VLSI Journal Vol. 64, pp. 29-39, 2019.
  23. Youngchan Kim and Taewhan Kim
    Synthesis and Exploration of Clock Spines
    IET Computers & Digital Techniques Vol. 12, No. 8, September 2018.
  24. Jeongwoo Heo and Taewhan Kim
    Circuit Timing Analysis and Optimization under Flexible Flip-flop Timing Model
    Journal of Semiconductor Technology and Science Vol. 7, No. 6, pp. 862-877, December 2017.
  25. Hyoungseok Moon and Taewhan Kim
    Loosely Coupled Multi-bit Flip-flop Allocation for Power Reduction
    Integration, the VLSI Journal, Vol. 58, pp. 125-133, June 2017.
  26. Deokjin Joo and Taewhan Kim
    Clock Buffer Polarity Assignment Under Useful Skew Constraints
    Integration, the VLSI Journal, Vol. 57, No. C, pp. 52-61, March 2017.
  27. Joohan Kim and Taewhan Kim
    Boundary Optimization of Buffered Clock Trees for Low Power
    Integration, the VLSI Journal, Vol. 56, No. C, pp. 86-95, January 2017.
  28. Juyeon Kim and Taewhan Kim
    Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 4, pp. 641-654, April 2017.
  29. Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, and Taewhan Kim
    Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage / Frequency Scaling
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35. No. 12, pp. 2068-2081, December, 2016.
  30. Hyoungjun Jeon and Taewhan Kim
    Gray-level Context-Driven Histogram Equalization
    IET Image Processing, Vol. 10, No. 5, pp. 349-358, May 2016.
  31. Juyeon Kim, Deokjin Joo, and Taewhan Kim
    Optimal Utilization of Adjustable Delay Clock Buffers for Timing Correction in Designs with Multiple Power Modes
    Integration, the VLSI Journal, Vol. 52, No. 1, pp. 91-101, January 2016.
  32. Hyoungjung Seo and Taewhan Kim
    Post Silicon Tuning Based on Flexible Flip-flop Timing
    Journal of Semiconductor Technology and Science, Vol. 16, No. 1, February 2016.
  33. Lu Cai and Taewhan Kim
    Context-Driven Hybrid Image Inpainting
    IET Image Processing, Vol. 9, No. 10, pp. 866-873, October 2015.
  34. Heechun Park and Taewhan Kim
    Synthesis of TSV Fault-Tolerant 3D Clock Trees
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 2, pp. 266-279, February 2015.
  35. Minseok Kang and Taewhan Kim
    Integrated Resource Allocation and Binding in Clock Mesh Synthesis
    ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 3, pp. 30:1-30:28, June 2014.
  36. Sangdo Park and Taewhan Kim
    Edge Layer Embedding Algorithm for Mitigating On-Package Variation in 3D Clock Tree Synthesis
    Integration, the VLSI Journal, Vol. 47, No. 4, pp. 476-486, September 2014.
  37. Byunghyun Lee and Taewhan Kim
    Algorithms for TSV Resource Sharing and Optimization in Designing 3D Stacked ICs
    Integration, the VLSI Journal, Vol. 47, No. 2, pp. 184-194, March 2014.
  38. Deokjin Joo and Taewhan Kim
    A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 3, pp. 423-436, March 2014.
  39. Kyoung-Hwan Lim, Deokjin Joo, and Taewhan Kim
    An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 3, pp. 392-405, March 2013.
  40. Tak-Yung Kim and Taewhan Kim
    Resource Allocation and Design Techniques of Pre-bond Testable 3D Clock Tree
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 138-151, January 2013.
  41. Jongyoon Jung and Taewhan Kim
    Statistical Viability Analysis for Detecting False Paths under Delay Variation
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 111-123, January 2013.
  42. Deokjin Joo, Minseok Kang, and Taewhan Kim
    Design Methodologies for Reliable Clock Networks
    Journal of Computing Science and Engineering, Vol. 6, No. 4, pp. 257-266, December 2012.
  43. Hyoungjung Seo, Jaewon Seo, and Taewhan Kim
    Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling
    The Computer Journal, Vol. 55, No. 11, pp. 1367-1382, November 2012.
  44. Jongyoon Jung and Taewhan Kim
    Variation Aware False Path Analysis Based on Statistical Dynamic Timing Analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.31, No.11, pp. 1684-1697, November 2012.
  45. Yonghwan Kim, Sanghoon Kwak, and Taewhan Kim
    Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
    ACM Transactions on Design Automation of Electronic Systems, Vol. 17, No. 4, pp. 43:1-43:29, October 2012.
  46. Tak-Yung Kim and Taewhan Kim
    Post Silicon Management of On-Package Variation Induced 3D Clock Skew
    Journal of Semiconductor Technology and Science, Vol. 12, No. 2, pp. 139-149, June 2012.
  47. Taewhan Kim
    Power Saving by Task-level Dynamic Voltage Scaling – A Theoretical Aspect in
    Book Chapter of Handbook of Energy-Aware and Green Computing, Chapman & Hall/CRC Computer & Information Science Series, Vol. 1, Edited by I. Ahmad and S. Ranka, January 2012.
  48. Tak-Yung Kim and Taewhan Kim
    Clock Tree Synthesis for TSV based 3D IC Designs
    ACM Transactions on Design Automation of Electronic Systems, Vol. 16, No. 4, pp. 48:1-48:21, October 2011.
  49. Yongho Lee, Deog-Kyoon Jeong, and Taewhan Kim
    Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits
    IEEE Transactions on VLSI Systems, Vol. 19, No. 3, pp. 494-498, March 2011.
  50. Yongho Lee and Taewhan Kim
    State Encoding Algorithm for Peak Current Minimization
    IET Computers & Digital Techniques, Vol. 5, No. 2, pp. 113-122, March 2011.
  51. Jongyoon Jung and Taewhan Kim
    Scheduling and Resource Binding Algorithm Considering Timing Variation
    IEEE Transactions on VLSI Systems, Vol. 19, No. 2, pp. 205-216, February 2011.
  52. Hochang Jang, Deokjin Joo, and Taewhan Kim
    Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 1, pp. 96-109, January 2011.
  53. Haneul Chon and Taewhan Kim
    Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC
    The Computer Journal, /Vol. 53, No. 7, pp. 883-894, September 2010.
  54. Taewhan Kim
    Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results
    Journal of Computing Science and Engineering, Vol. 4, No. 3, pp. 189-206, September 2010.
  55. Seungwhun Paik, Insup Shin, Taewhan Kim, and Youngsoo Shin
    HLS-l: A High-level Synthesis Framework for Latch-based Architectures
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, pp. 657-670, May 2010.
  56. Byunghyun Lee, Ki-seok Chung, Bontae Koo, Nak-woong Eum, and Taewhan Kim
    Thermal Sensor Allocation and Placement for Reconfigurable Systems
    ACM Transactions on Design Automation of Electronic Systems, Vol. 14, No. 4, August 2009.
  57. Pilok Lim, Ki-seok Chung, and Taewhan Kim
    Thermal-Aware High-level Synthesis Based on Network Flow Method
    Journal of Circuits, Systems and Computers, Vol. 18, No. 5, pp. 965-984, 2009.
  58. Kyung-Hwan Lim, YongHwan Kim, and Taewhan Kim
    Interconnect and Communication Synthesis for Distributed Register-File Micro-architecture
    IET Computers & Digital Techniques, Vol.3, No.2, pp. 162-174, March 2009.
  59. Benjamin Carrion Schafer and Taewhan Kim
    Autonomous Temperature Control Technique in VLSI Circuits Through Logic Replication
    IET Computers & Digital Techniques, Vol.3, No.1, pp. 62-71, January 2009.
  60. Benjamin Carrion Schafer and Taewhan Kim
    Hotspots Elimination and Temperature Flattening in VLSI Circuits
    IEEE Transactions on VLSI Systems, Vol. 16, No. 11, pp. 1475-1487, November 2008
  61. Yunheung Paek, Minook Ahn, Doosan Cho, and Taewhan Kim
    Efficient Embedded Code Generation with Multiple Load/Store Instructions
    Software-Practice & Experience, Vol. 37, No. 11, pp. 1133-1159, September 2007.
  62. Yongseok Choi, Naehyuck Chang and Taewhan Kim
    DC-DC Converter-Aware Power Management for Low-Power Embedded Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 8, pp. 1367-1381, 2007.
  63. Taewhan Kim and Jungeun Kim
    Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory Access Optimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 1, pp. 142-151, January 2007.
  64. Jong-U Shin and Taewhan Kim
    Technique for Transition Energy-Aware Dynamic Voltage Assignment
    IEEE Transactions on Integrated Circuits and Systems II, Vol. 53, No. 9, pp. 956-960, September 2006.
  65. Junhyung Um and Taewhan Kim
    Resource Sharing Combined with Layout Effects in High-Level Synthesis
    Journal of VLSI Signal Processing, Vol. 44, No. 3, pp. 231-243, September 2006.
  66. Young-Jun Kim and Taewhan Kim
    A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications
    Journal of VLSI Signal Processing, Vol. 44, No. 3, pp. 269-283, September 2006.
  67. Yoonseo Choi and Taewhan Kim
    Memory Access Driven Storage Assignment for Variables in Embedded System Design
    Journal of Circuits, Systems and Computers, Vol. 15, No. 2, pp. 145-168, April 2006.
  68. Chun-Gi Lyuh and Taewhan Kim
    Low Power Bus Encoding with Crosstalk Delay Elimination
    IET Computers & Digital Techniques, Vol. 153, No. 2, pp. 93-100, March 2006.
  69. Chun-Gi Lyuh and Taewhan Kim
    Memory Access Scheduling and Binding Considering Energy Minimization in Multi-Bank Memory Systems: An Integrated Approach
    IET Computers & Digital Techniques, Vol. 153, No. 1, pp. 59-68, January 2006.
  70. Jaewon Seo, Taewhan Kim and Joonwon Lee
    Optimal Intra-Task Dynamic Voltage Scaling and Its Practical Extensions
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 1, pp. 47-57, January 2006.
  71. Woo-Cheol Kwon and Taewhan Kim
    Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors
    ACM Transactions on Embedded Computing Systems, Vol. 4, No. 1, pp. 211-230, February 2005.
  72. Yoonseo Choi, Taewhan Kim, and Hwansoo Han
    Memory Layout Techniques for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 2, pp. 278-287, February 2005.
  73. Keoncheol Shin and Taewhan Kim
    Tight Integration of Timing-Driven Synthesis and Placement of Parallel Multiplier Circuits
    IEEE Transactions on VLSI Systems, Vol. 12, No. 7, pp. 766-775, July 2004.
  74. Nak-Woong Eum, Taewhan Kim, and Chong-Min Kyung
    CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
    IEEE Transactions on Computers, Vol. 53, No. 7, pp. 829-842, July 2004.
  75. Keoncheol Shin and Taewhan Kim
    Leakage Power Minimization in Arithmetic Circuits
    IEE Electronics Letters, Vol. 40, No. 7, pp. 415-417, April 2004.
  76. Chun-Gi Lyuh, Taewhan Kim and Ki-Wook Kim
    Coupling-Aware High-Level Interconnect Synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 1, pp. 157-164, January 2004.
  77. Junhynung Um and Taewhan Kim
    Synthesis of Arithmetic Circuits Considering Layout Effects
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 11, pp. 1487-1503, November 2003.
  78. Jaewon Seo, Taewhan Kim, and Preeti R. Panda
    Memory Allocation and Mapping in High-level Synthesis: An Integrated Approach
    IEEE Transactions on VLSI Systems, Vol. 11, No. 5, pp. 928-938, October 2003.
  79. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu and Sung-Mo Kang
    Coupling Delay Optimization by Temporal Decorelation using Dual Threshold Voltage Technique
    IEEE Transactions on VLSI Systems, Vol. 11, No. 5, pp. 879-887, October 2003.
  80. Yoonseo Choi and Taewhan Kim
    Address Assignment in DSP Code Generation – An Integrated Approach
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 22, No. 8, pp. 976-984, August 2003.
  81. Chun-Gi Lyuh and Taewhan Kim
    High-level Synthesis for Low-Power Based on Network Flow Method
    IEEE Transactions on VLSI Systems, Vol. 11, No. 3, pp. 364-375, June 2003.
  82. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, and Sung-Mo Kang
    Minimum Delay Optimization for Domino Logic Circuits: A Coupling-Aware Approach
    ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 2, pp. 203-213, April 2003.
  83. Sungpack Hong and Taewhan Kim
    Bus Optimization for Low Power in High-level Synthesis
    Journal of Circuits, Systems and Computers, Vol. 12, No. 1, pp. 1-16, Feb. 2003.
  84. Ki-Seok Chung, Rajesh Gupta, Taewhan Kim and C. L. Liu
    Synthesis and Optimization of Combinational Interface Circuits
    Journal of VLSI Signal Processing, Vol. 31, No. 2, pp. 243-261, July 2002.
  85. Yoonseo Choi and Taewhan Kim
    Binding Algorithm for Power Optimization Based on Network Flow Method
    Journal of Circuits, Systems and Computers, Vol. 11, No. 3, pp. 259-272, June 2002.
  86. Ki-Seok Chung, Taewhan Kim, and C. L. Liu
    A Complete Model for Glitch Analysis in Logic Circuits
    Journal of Circuits, Systems and Computers, Vol. 11, No. 2, pp. 137-154, Apr. 2002.
  87. Ki-Wook Kim, Taewhan Kim, Ting-Ting Hwang, C. L. Liu, and Sung-Mo Kang
    Logic Transformation for Low Power Synthesis
    ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 2, pp. 265-283, Apr. 2002.
  88. Ki-Wook Kim, Taewhan Kim, C. L. Liu, and Sung-Mo Kang
    Domino Logic Synthesis based on Implication Graph for Set of Mandatory Assignments
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 21, No. 2, pp. 232-240, Feb. 2002.
  89. Priyadarsan Patra, Unni Narayanan, and Taewhan Kim
    Phase Assignment for the Synthesis of Low Power Domino Circuits
    Electronics Letter, Vol. 37, No. 13, pp. 814-816, June 2001.
  90. Ki-Wook Kim, Seoong-Ook Jung, Taewhan Kim and Sung-Mo Kang
    Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits.
    Eletronics Letter, Vol.37, No.13, pp. 813-814, June 2001.
  91. Junhyung Um and Taewhan Kim
    An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.
    IEEE Transactions on Computers, Vol.50, No.3, pp. 215-233, March 2001.
  92. Ki-Seok Chung, Taewhan Kim and C.L.Liu
    G-vector: A New Model for Glitch Analysis in Logic Circuits.
    Journal of VLSI Signal Processing, Vol.27, No.3, pp. 235-252, March 2001.
  93. Sungpack Hong, Unni NArayanan,Ki-Seok Chung and Taewhan Kim
    Decompostion of Bus-invert Coding for Low-Power I/O
    Journal of Circuits, System and computers, Vol.10, No.1-2, pp.101-111, 2000.
  94. Youngtae Kim and Taewhan
    Accurate Exploration of Timing and Area Trade-offs in Arithmetic Optimization using Carry-Save-Adders
    Journal of Circuits, Systems and Computers, Vol. 10, No. 5 & 6, pp. 279-292, October & December 2000.
  95. Chaeryung Park, Taewhan Kim, and C. L. Liu
    An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization
    VLSI Design, Vol. 11, No. 4, pp. 381-396, 2000.
  96. Ki-Seok Chung, Taewhan Kim, and C. L. Liu
    Power Optimization of Multi-Level Logic Circuits Utilizing Circuit Symmetries
    International Journal of Electronics, Vol. 87, No. 7, pp. 841-852, July 2000.
  97. Taewhan Kim and Junhyung Um
    A Practical Approach to the Synthesis of Arithmetic Circuits using Carry-Save-Adders
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 19, No. 5, pp. 615-624, May 2000.
  98. Junhyung Um and Taewhan Kim
    Optimal Bit-level Arithmetic Optimization for High-Speed Circuits
    Electronics Letter, Vol. 36, No. 5, pp. 405-407, March 2000.
  99. Taewhan Kim, Ki-Seok Chung, and C. L. Liu
    A Stepwise Refinement Synthesis of Digital Systems for Testability Enhancement
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E82-A, No. 6, pp. 1070-1081, June 1999.
  100. Taewhan Kim, William Jao, and Steve Tjiang
    Circuit Optimization using Carry-Save-Adder Cells
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 17, No. 10, pp. 974-984, October 1998.
  101. Chaeryung Park, Taewhan Kim, and C. L. Liu
    Register Allocation – Hierarchical Reduction Approach
    Journal of VLSI Signal Processing, Vol. 19, No. 3, pp. 269-289, August 1998.
  102. Taewhan Kim and C. L. Liu
    An Integrated Algorithm for Incremental Data Path Synthesis
    Journal of VLSI Signal Processing, Vol. 12, No. 3, pp. 265-285, June 1996.
  103. Taewhan Kim and C. L. Liu
    A New Approach to the Multiport Memory Allocation Problem in Data Path Synthesis
    the VLSI Journal, INTEGRATION, Vol. 19, No. 3, pp. 133-160, 1995.
  104. Hideroni Nakazato, Jane W. S. Liu, and Taewhan Kim
    A Scheduling Strategy for Tasks with Precedence and Conditional Execution
    Transactions of Information Processing Society of Japan, Vol. 36, No. 9, pp. 2161-2174, September 1995.
  105. Taewhan Kim, Noritake Yonezawa, Jane W. S. Liu, and C. L. Liu
    A Scheduling Algorithm for Conditional Resource Sharing – A Hierarchical Reduction Approach
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 13, No. 4, pp. 425-438, April 1994.

Domestic Journals

  1. 김탁영, 김태환
    Physical Design for 3D Integrated Circuits
    대한전자공학회지 (The Magazine of IEEK), Vol. 36, No. 9, pp. 969-979, September 2009.
  2. 김영준, 김태환
    멀티모드 멀티태스크 임베디드 어플리케이션을 위한 HW/SW 분할 기법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 34, No. 7.8, pp. 337-347, August 2007.
  3. 최윤서, 김태환
    임베디드 시스템 설계에서 효율적인 메모리 접근을 고려한 변수 저장 방법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 32, No. 1.2, pp. 85-94, February 2005.
  4. 정기석, 김태환
    회로의 대칭성을 이용한 다단계 논리회로에서의 전력 소모 최소화 기법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 30, No. 9.10, pp. 504-511, October 2003.
  5. 서재원, 김태환, 정기석
    분산된 VLIW 구조에서의 최대 전력 최소화 방법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 30, No. 5.6, pp. 258-264, June 2003.
  6. 여준기, 김태환
    저전력과 크로스톡 지연 제거를 위한 버스 인코딩
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 29, No. 11.12, pp. 680-686, December 2002.
  7. 정기석, 김태환
    내장형 시스템 설계: 개론
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 20, No. 7, pp. 5-13, July 2002.
  8. 김태환, 정기석
    개선된 테스트 용이화를 위한 점진적 개선 방식의 데이터 경로 합성 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 29, No. 5.6, pp. 361-368, June 2002.
  9. 김태환, 엄준형
    캐리-세이브 가산기에 기초한 연산 하드웨어 최적화를 위한 실질적 합성 기법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 28, No. 9.10, pp. 520-529, October 2001.
  10. 김태환
    조건부 분기를 가진 데이터-흐름 그래프 스케줄링 알고리즘:변형을 통한 방법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 28, No. 1-2, pp. 103-109, February 2001.
  11. 홍성백, 김태환
    저전력을 위한 버스-인버트 코딩 분할 기법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 28, No. 1-2, pp. 52-57, February 2001.
  12. 김태환
    네트워크-플로우 방법을 기반한 통합적 데이터-경로 합성 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 27, No. 12, pp. 981-987, December 2000.
  13. 김태환, 홍성백
    데이터 경로 합성에서의 연결선 최적화를 위한 다중포트 메모리 할당 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 27, No. 9, pp. 816-823, September 2000.
  14. 박채령, 김영태, 김태환
    상위 단계에서의 효율적인 저전력 데이터-경로 합성 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 27, No. 2, pp. 227-233, February 2000.
  15. 엄준형, 김태환
    회로 최적화를 위한 캐리-세이브 가산기 할당 알고리즘
    정보 과학회 컴퓨터 이론 연구회지 (SIGTCS), Vol. 10, No. 2, pp. 2-19, December 1999.
  16. 엄준형, 김태환
    캐리-세이브 가산기를 이용한 연산 최적화 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 26, No. 12, pp. 1539-1547, December 1999.
  17. 김태환, 엄준형
    VLSI 설계에서 캐리-세이브 가산기를 이용한 설계블럭들 간의 최적화
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 26, No. 5, pp. 620-626, May 1999.
last modified 2024-09-14 09:16