Prof. Taewhan Kim

Contact Information

  • email: tkim AT ssl.snu.ac.kr
  • phone: 02-880-9133
  • fax: 02-878-1452
  • address: School of Electrical Engineering and Computer Science, Seoul National Univ., 599 Gwanak-gu, 151-744, Seoul, Korea
  • lab: http://snucad.snu.ac.kr

Research Area

  • Big Data Analytics (active)
  • Neural Network Architectures (active)
  • Reliable and Variation-Aware Logic/Physical Design (active)
  • Display Images and Embedded Software (active)
  • 3D IC Design
    • 3D physical design
    • 3D clock path synthesis
    • 3D power network delivery
    • Flip-chip router, 3D timing analysis
    • 3D thermal analysis and management
  • Embedded Systems
    • Compilation techniques: Leakage power aware instruction generation
    • Software platform design for multimedia/wireless applications
    • Simulation and GUI environment tool for reconfigurable processor
    • Code generation technique for leakage cache power minimization
    • Multi-banks code access optimization
    • DRAM memory access code optimization
    • Address code generation for DSP-oriented processors
    • Low-energy variable partitioning/scheduling for embedded processor with multiple banks
    • Low-energy task/voltage scheduling (OS) for real-time embedded systems
    • Data arrangements in DRAMs for access optimization
    • Cache activity optimization for hard real-time embedded systems
    • Low-power resource constrained bus encoding
    • Voltage scheduling and allocation
    • Access code optimization for embedded systems with multiple banks
    • Low-energy code compression
  • Thermal-Aware Design
    • Thermal simulator tool
    • Thermal-aware floorplanning
    • Thermal-aware architecture/logic synthesis
    • Logic synthesis for leakage current minimization
    • Voltage island
  • Architecture-Level Synthesis for System-on-Chip design
    • Leakage-aware bus encode
    • Interconnect/coupling-aware synthesis
    • Unified (fabric-driven) synthesis and placement
    • ALU design and arithmetic optimization
    • Synthesis for low-power design architecture
    • Leakage power optimization
  • Logic-Level Synthesis
    • Variation-aware false path analysis
    • Synthesis/analysis for low-power logic circuit
    • System (interface) synthesis
  • High-Level Synthesis
    • High-level synthesis for 3D IC design
    • Synthesis for low power
    • Memory synthesis
    • Scheduling/allocation/testability for timing/area
  • PhD Thesis
    • Scheduling and Allocation Problems in High-level Synthesis (advisor: C. L. Liu, Univ. of Illinois at U-C)

Work Experience

Education

  • PhD, Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1988.8 – 1993.10
  • M.S., Dept of Computer Science and Statistics, Seoul National University, 1985.3 – 1987.2
  • B.S., Dept. of Computer Science and Statistics, Seoul National University, 1981.3 – 1985.2

Publications

Journals
Conferences

Teaching Courses

  • 컴퓨터 개념 및 실습 (2017 봄 학기)

Students

  • Joohan Kim (김주한) (MS, 2010.3 – 2012.2, PhD, 2012.3 – )
  • Park, Hee-chun(박희천) (MS+PhD, 2011.3 – )
  • Kim, YoungChan (김영찬) (MS, 2011.3 – 2013.2, PhD, 2013.3 – )
  • Kim, Juyeon (김주연) (MS+PhD, 2013.3 – )
  • Ahn, Seyong (안세용) (MS+PhD, 2013.3 – )
  • Heo, Jeongwoo (허정우) (MS+PhD, 2014.3 – )
  • Kang, Jongsung (강종성) (MS+PhD, 2014.3 – )
  • Moon, Hyungseok (문형석) (PhD, 2014.3 – )
  • Ahn, Byungmin (안병민) (MS+PhD, 2015.3 – )
  • Gyounghwan (현경환) (PhD, 2016.3 – )
  • Seongkwan (이성관) (MS, 2016.3 – )
  • Cho, WooHyeong (조우형) (MS+PhD, 2016.3 – )
  • Jo, Kyeong rok (조경록) (MS+PhD, 2016.3 – )
  • Kim, Tae Hwan (김태환) (MS+PhD, 2016.3 – )
  • Park, Jungwon (박중원) (MS+PhD, 2016.3 – )
  • Sun, Hongyang (손홍양) (MS, 2016.9 – )

Alumni

  • 이동윤 (Dongyoun Yi) (MS, 2015.3 – 2017.2) (Samsung Electronics):
    Flip-flop and Power-gated Cell Optimization for Modern SoC Designs
  • 전형준 (Hyungjun Jeon) (MS, 2008.3 – 2010.2, PhD, 2013.3 – 2017.2) (Samsung Electronics):
    Algorithms for Histogram Equalization in Image Enhancement and Link Prediction in Social Networks
  • 주덕진 (Deok-jin Joo) (MS, 2009.3 – 2011.2, PhD, 2011.9 – 2016.2) (Post-Doc at Univ. of Illinois):
    Clock Polarity Assignment Methodologies for Designing High-Performance and Robust Clock Trees
  • 서형중 (Hyeoungjung Seo) (MS, 2009.3 – 2011.2, PhD, 2011.3 – 2015.8) (Samsung Electronics):
    Design Methodology for Reliable Clock Networks for High-Speed and Low-Power Digital Systems
  • 재옥 (Lu, Cai) (MS, 2013.9 – 2015.8) (Oracle, China):
    Context-Driven Image Inpainting
  • 강민석 (Minseok Kang) (MS, 2008.3 – 2010.2, PhD, 2010.3 – 2015.2) (Samsung Electronics):
    Methodology for Clock Mesh Synthesis
  • 이명우 (Myoungwoo Lee) (MS, 2012.3 – 2014.2) (Samsung Electronics):
    A Linear Time Algorithm of Low Power Histogram Equalization of OLED Displays
  • 박기태 (Kitae Park) (MS, 2012.3 – 2014.2) (Venture, Embedded Software):
    Utilization of Multiple Types of Adjustable Delay Buffers for Resolving Clock Timing Violation
  • 김근호 (Geunho Kim) (MS, 2012.3 – 2014.2) (Agency for Defence Development) :
    Analysis on Adjustable Delay Buffer Design and Control Circuit for Multiple Power Mode Designs
  • 박상도 (Sangdo Park) (MS, 2007.9 – 2009.8, PhD, 2009.9 – 2014.2) (Samsung Electronics):
    Variation Aware Design and Packaging Problems in 3D ICs
  • 정종윤 (JongYoon Jung) (MS, 2006.3 – 2008.2, PhD, 2008.3 – 2012.2) (Samsung Electronics):
    Algorithms for False Path Aware Statistical Timing Analysis
  • 이병현 (ByungHyun Lee) (MS, 2006.3 – 2008.2, PhD, 2008.3 – 2012.2) (Samsung Electronics):
    Partitioning and TSV Optimization Algorithms for 3D IC Design
  • 김용환 (YongHwan Kim) (MS, 2005.3 – 2007.2, PhD, 2007.3 – 2012.2) (Samsung Electronics):
    Synthesis of Hybrid Adders for Timing Optimization
  • 김기영 (Kim, Kiyoung) (MS, 2010.3 – 2012.2) (TMAX):
    Algorithm for Synthesizing Design Context-Aware Fast Carry-Skip Adders
  • 구준모 (Koo, Joon-Mo) (MS, 2010.3 – 2012.8) (SK-Hynix):
    Code Generation Technique for Mitigating Soft Errors in Memory Accesses
  • 김탁영 (Tak-Yung Kim) (PhD, 2009.3 – 2012.2) (Samsung Electronics):
    Design Methology of Clock Networks for TSV Based 3D IC Designs
  • 임경환 (Kyung-Hwan Lim) (MS, 2005.3 – 2007.2, PhD, 2007.3 – 2012.2) (Samsung Electronics):
    Design Methodology of Reliable Clock Network Based on Adjustable Delay Buffers
  • 박단비 (DanBee Park) (MS, 2009.3 – 2011.2) (SAP):
    Optimal Algorithm for Profile-Based Power Gating: A Compiler Technique for Reducing Leakage Power on Execution Units in Microprocessors
  • 임필옥 (Pilok Lim) (PhD, 2005.3 – 2010.12, off: 2007.9 – 2008.8) (Sejong University)
    Temperature-aware Resource Binding Problems in High-level Synthesis
  • 김한준 (HanJun Kim) (MS, 2008.9 – 2011.8):
    NBTI-aware leakage current minimization technique
  • 곽상훈 (Sanghun Kwak) (PostDoC, 2009.8 – 2010.10)
    Synthesis of arithmetic circuits
  • 이용호 (YongHo Lee) (PhD, 2006.9 – 2010.8) (Samsung Electronics):
    Design methodologies for peak current and NBTI controlled logic circuits
  • 전형준 (HyungJun Jeon) (MS, 2008.3 – 2010.2) (Venture, Embedded Software):
    Routing algorithm for flip-chip design
  • Benjamin Schaefer (PostDoc, 2007.3 – 2008.8) (HK Polytechnic University)
    Thermal-aware chip design
  • 장호창 (Hochang Jang) (MS, 2007.3 – 2009.2) (Consultat, Patent agent):
    Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization
  • 전하늘 (Haneul Chun) (MS, 2007.3 – 2009.2) (Samsung Electronics):
    Timing variation-aware task scheduling and binding in MPSoC
  • 유예신 (Yehshin Ryu) (MS, 2006.9 – 2008.8) (Samsung Electronics):
    Clock polarity assignment combined with clock tree generation
  • 김기남 (Kinam Kim, MS, 2004.9 – 2006.8) (LG Electronics):
    Thermal-aware loop scheduling in high-level synthesis
  • 이전민 (Zhenmin Li, MS, 2004.9 – 2006.8, Samsung GSP Program) (Samsung Electronics):
    Address code optimization exploiting code scheduling in DSP applications
  • 김영준 (Young-Jun Kim, MS, 2004.3 – 2006.2) (Samsung Electronics):
    A HW/SW partitioner for multi-mode multi-task embedded applications
  • 여준기 (Chun-Gi Lyuh, PhD, 2000.3 – 2004.2) (ETRI):
    Low-power synthesis problems in system-on-chip designs
  • 엄준형 (Junhyung Um, PhD, 1999.3 – 2003.2) (Samsung Electronics):
    High-performance and reliable architecture synthesis problems in system-on-chip design
  • 차미영 (Meeyoung Cha, MS, 2002.3 – 2004.2) (KAIST PhD):
    Resource-constrained low-power bus encoding in embedded system design
  • 신건철 (Keoncheol Shin, MS, 2002.3 – 2004.2) (KAIST PhD) (Samsung Electronics):
    Synthesis of arithmetic circuits considering leakage power minimization
  • 최윤서 (Yoonseo Choi, MS/PhD(KAIST), 2000.3 – 2006.12) (IBM-Waston, Samsung Technology and Science):
    An efficient binding algorithm in data path synthesis utilizing network flow computation
  • 서재원 (Jaewon Seo, MS/PhD(KAIST), 2000.3 – 2005.5) (Google):
    Optimal Intra-task Dynamic Voltage Scaling Techniques and Its Practical Extensions
  • 홍성백 (Sungpaek Hong, MS, 1999.3 – 2001.2) (Stanford for PhD):
    A study on bus synthesis for low-power in VLSI system design
  • 김영태 (Youngtae Kim, MS, 1999.3 – 2001.2) (TMAX):
    Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders

Activities and Awards

  1. Education Award (교육상), Seoul National University, November 2016
  2. Teaching Excellence Award (우수 강의상), School of Electrical Engineering, Seoul National University, February 2016
  3. Research Excellence Faculty Award (우수 연구상), College of Engineering, Seoul National University, February 2014
  4. Invited Talk
    “Design Methodology for Robust Clock Networks,” National Taiwan University, February 2014
  5. Associate Editor
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2014 – present
  6. Associate Editor
    Integration – VLSI Journal, January 2014 – present
  7. Best Paper Award
    B. Lee and T. Kim, “High-level TSV Resource Sharing and Optimization for TSV Based 3D IC Designs,”
    IEEE International System-on-Chip Conference (SOCC), September 2013
  8. Tutorial Speaker
    “Methodology for Designing Reliable Clock Networks,” IEEE International System-on-Chip Conference, September 2013
  9. Tutorial Speaker
    “Design Methodology for Robust Clock Networks,” IEEE Midwest Symposium on Circuits and Systems, August 2013
  10. Invited Talk
    “Design Methodology for Robust Clock Networks,” LG Electronics Company, August 2013
  11. Invited Talk
    “Synthesis Problems for Reliable Clock Network Design,” EECS, University of Michigan – Ann Arbor, January 2013
  12. Invited Talk
    “Thermal Management Techniques,” Samsung Elecrobics Company, November 2011
  13. Best Paper Award
    P. Lim and T. Kim, “Thermal-Aware Resource Rebinding Algorithm for Timing Optimization in 3D IC Designs,” IEEE International SOC Design Conference (ISOCC), November 2010
  14. Tutorial Chair
    IEEE International Asia and South Pacific Design Automation Conference (ASPDAC), January 2008
  15. General Chair
    ACM International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES), October, 2007
  16. General Chair
    IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), August, 2007
  17. Program Chair
    ACM International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES), October, 2006
  18. Shin-yang Research Excellence Award (신양 학술상), November 2006
  19. Nomination for Best Paper Award
    W. Kwon and T. Kim, “Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors,” IEEE/ACM Design Automation Conference (DAC), June 2003
last modified 2017-01-25 11:28