People

M.S. Students

Interns

Alumni

• 김수완 (Suwan Kim) (PhD, 2019.9 - 2024.8) (Samsung Advanced Institute of Technology):
  Methodologies of Utilizing Design Enablement Resources for High-Quality Physical Design

• 정세현 (Sehyeon Chung) (PhD, 2019.3 - 2024.8) (Samsung Electronics):
  Physical Design Enablement Solutions Coupled with Design and Technology Co-optimization

• 정은솔 (Eunsol Jeong) (PhD, 2018.8 - 2024.8) (Samsung Electronics):
  Physical Design Flow Optimizations Considering MIA Design Rules and 3D ICs

• 장경준 (Kyung Joon Chang) (PhD, 2018.3 - 2024.8) (Samsung Electronics):
  Machine Learning Based Timing Prediction and Optimization Methodologies in Physical Design

• 김화평 (Hwapyong Kim) (MS, 2022.3 – 2024.2) (Samsung Electronics):
  Refining Algorithms for Placement Legalization and Global Routing

• 양재완 (Jaewan Yang) (MS, 2022.3 – 2024.2) (Samsung Electronics):
  Design Methodologies for Timing-aware Multi-bit Flip-flop Allocation and Physical Design Parameter Optimization

• 김수민 (Soomin Kim) (PhD, 2018.3 – 2023.8) (Samsung Electronics):
  Storage Synthesis and Optimization Algorithms for High-speed and Low-power Chips

• 백경현 (Kyeonghyeon Baek) (PhD, 2017.3 – 2023.2) (Samsung Electronics):
  Synthesis and Optimization of Standard Cells and Design Quality Prediction in Physical Design Automation

• 박소라 (Sora Park) (MS, 2021.3 – 2023.2) (Samsung Electronics):
  Synthesis of Clock Gating Based on Accurate and Learning Driven Power Analyses

• 조경록 (Kyeongrok Jo) (PhD, 2016.3 – 2021.8) (Samsung Electronics):
  Methodologies for Standard Cell Generation and Design Rule Evaluation

• 김태환 (Taehwan Kim) (PhD, 2016.3 – 2021.8) (Samsung Electronics):
  Voltage and Retention Storage Allocation Problems for SRAMs and Power Gated Circuits

• 안병민 (Byungmin Ahn) (PhD, 2015.3 – 2021.2) (Samsung Electronics):
  Memory Layout and Computing Techniques for High Performance Neural Networks

• 허정우 (Jeongwoo Heo) (PhD, 2014.3 – 2020.8) (Samsung Electronics):
  Timing Analysis and Optimization in Logic and Physical Synthesis

• 강종성 (Jongsung Kang) (PhD, 2014.3 – 2020.8) (Samsung Electronics):
  Design of High Performance Computing Units for On-device Neural Network Accelerators

• 황은실 (Eunsil Hwang) (MS, 2017.3 – 2020.8) (Samsung Electronics):
  Optimization of State Retention Storage and the Control Signal on Power Gated circuits

• 현경환 (Gyounghwan Hyun) (PhD, 2016.3 – 2020.2) (Samsung Electronics):
  Design Methodology for Cost Effective Clock and Power Gating

• 양기용 (Giyoung Yang) (MS, 2017.3 - 2019.2) (Samsung Electronics):
  Design and algorithm for clock gating and flip flop optimization

• 손홍양 (Hongyang Sun) (MS, 2016.9 - 2019.2) (Solugate):
  Neural Model for Named Entity Recognition Considering Aligned Representation

• 박중원 (Jungwon Park) (MS, 2016.3 - 2019.2):
  Training method of branch network optimized for simple inputs

• 안세용 (Seyong Ahn) (PhD, 2013.3 – 2018.8) (Samsung Electronics):
  Studies on Resonant Clock Network Synthesis and Design Technology Co-Optimization Framework

• 조우형 (Woohyeong Cho) (MS, 2016.3 – 2018.2) (TMAX):
  Technique of Removing Redundant Neurons for Compressing Deep Neural Networks

• 이성관 (Seongkwan Lee) (MS, 2016.3 – 2018.2) (Samsung Electronics):
  Cost Effective Technique for Diagnosing Clock on FPGAs

• 문형석 (Hyungsuk Moon) (PhD, 2014.3 – 2018.2) (Samsung Electronics):
  Design Methodolgies using Multi-bit Flip-flops for Low power

• 김주연 (Juyeon Kim) (PhD, 2013.3 – 2018.2) (Samsung Electronics):
  Methodolgy for Solving Timing Closure Problem by Utilizing Adjustable Clock Buffers

• 김영찬 (Youngchan Kim) (MS, 2011.3 – 2013.2, PhD, 2013.3 – 2018.2) (Samsung Electronics):
  Algorithm for Synthesizing Clock Spine Networks

• 박희천 (Hee-chun Park) (PhD, 2011.3 – 2018.2) (Professor Kookmin Univ.):
  Circuit and Architectural Optimization for Emerging High-speed and Computing Technologies

• 김주한 (Joohan Kim) (MS, 2010.3 – 2012.2, PhD, 2012.3 – 2017.8) (Samsung Electronics):
  Clock Buffer and Flip-flop Co-optimization for Reducing Power Consumption and Peak Current Noise

• 이동윤 (Dongyoun Yi) (MS, 2015.3 – 2017.2) (Samsung Electronics):
  Flip-flop and Power-gated Cell Optimization for Modern SoC Designs

• 전형준 (Hyungjun Jeon) (MS, 2008.3 – 2010.2, PhD, 2013.3 – 2017.2) (Samsung Electronics):
  Algorithms for Histogram Equalization in Image Enhancement and Link Prediction in Social Networks

• 주덕진 (Deok-jin Joo) (MS, 2009.3 – 2011.2, PhD, 2011.9 – 2016.2) (Post-Doc at Univ. of Illinois):
  Clock Polarity Assignment Methodologies for Designing High-Performance and Robust Clock Trees

• 김기영 (Kiyoung Kim) (MS, 2010.3 – 2012.2, PhD, 2012.3 – 2015.12) (TMAX):
  Algorithm for Synthesizing Design Context-Aware Fast Carry-Skip Adders

• 서형중 (Hyeoungjung Seo) (MS, 2009.3 – 2011.2, PhD, 2011.3 – 2015.8) (Samsung Electronics):
  Design Methodology for Reliable Clock Networks for High-Speed and Low-Power Digital Systems

• 재옥 (Lu, Cai) (MS, 2013.9 – 2015.8) (Oracle, China):
  Context-Driven Image Inpainting

• 강민석 (Minseok Kang) (MS, 2008.3 - 2010.2, PhD, 2010.3 - 2015.2) (Samsung Electronics):
  Design Methodology for Mesh Based Clock Networks

• 김근호 (Geunho Kim) (MS, 2012.3 - 2014.2):
  Analysis on Adjustable Delay Buffer Design and Control Circuit for Multiple Power Mode Designs

• 박기태 (Kitae Park) (MS, 2012.3 - 2014.2) (Altibase):
  Utilization of Multiple Types of Adjustable Delay Buffers for Resolving Clock Timing Violation

• 이명우 (Myungwoo Lee) (MS, 2012.3 - 2014.2) (Samsung Display):
  A Linear Time Algorithm of Low Power Histogram Equalization of OLED Displays

• 박상도 (Sangdo Park) (MS, 2007.9 - 2009.8, PhD, 2009.9 - 2014.2) (Samsung Electronics):
  Variation Aware Design and Packaging Problmes in 3D ICs

• 정종윤 (JongYoon Jung) (MS, 2006.3 - 2008.2, PhD, 2008.3 - 2012.2) (Samsung Electronics):
  Algorithms for False Path Aware Statistical Timing Analysis

• 이병현 (ByungHyun Lee) (MS, 2006.3 - 2008.2, PhD, 2008.3 - 2012.2) (Samsung Electronics):
  Partitioning and TSV Optimization Algorithms for 3D IC Design

• 김용환 (YongHwan Kim) (MS, 2005.3 - 2007.2, PhD, 2007.3 - 2012.2) (Samsung Electronics):
  Synthesis of Hybrid Adders for Timing Optimization

• 구준모 (Koo, Joon-Mo) (MS, 2010.3 - 2012.8):
  Code Generation Technique for Mitigating Soft Errors in Memory Accesses

• 김탁영 (Tak-Yung Kim) (PhD, 2009.3 - 2012.2) (Samsung Electronics):
  Design Methology of Clock Networks for TSV Based 3D IC Designs

• 임경환 (Kyung-Hwan Lim) (MS, 2005.3 - 2007.2, PhD, 2007.3 - 2012.2) (Samsung Electronics):
  Design Methodology of Reliable Clock Network Based on Adjustable Delay Buffers

• 박단비 (DanBee Park) (MS, 2009.3 - 2011.2) (SAP Korea):
  Optimal Algorithm for Profile-Based Power Gating: A Compiler Technique for Reducing Leakage Power on Execution Units in Microprocessors

• 임필옥 (Pilok Lim) (PhD, 2005.3 – 2010.12, off: 2007.9 – 2008.8):
  Temperature-aware resource binding problems in high-level synthesis

• 김한준 (HanJun Kim) (MS, 2008.9 – 2011.8):
  NBTI-aware leakage current minimization technique

• 곽상훈 (Sanghun Kwak) (PostDoC, 2009.8 – 2010.10)

• 이용호 (YongHo Lee) (PhD, 2006.9 – 2010.8) (Samsung Electronics):
  Design methodologies for peak current and NBTI controlled logic circuits

• 전형준 (HyungJun Jeon) (MS, 2008.3 – 2010.2) (Venture, Embedded Software):
  Routing algorithm for flip-chip design)

• Benjamin Schaefer (PostDoc, 2007.3 – 2008.8) (NEC, Japan)

• 장호창 (Hochang Jang) (MS, 2007.3 – 2009.2) (Consultant):
  Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization

• 전하늘 (Haneul Chun) (MS, 2007.3 – 2009.2) (Intel):
  Timing variation-aware task scheduling and binding in MPSoC

• 유예신 (Yehshin Ryu) (MS, 2006.9 – 2008.8) (Samsung Electronics):
  Clock polarity assignment combined with clock tree generation

• 김기남 (Kinam Kim, MS, 2004.9 – 2006.8) (LG Electronics):
  Thermal-aware loop scheduling in high-level synthesis

• 이전민 (Zhenmin Li, MS, 2004.9 – 2006.8, Samsung GSP Program) (Samsung Electronics):
  Address code optimization exploiting code scheduling in DSP applications