Publications

International Journals

  1. Suwan Kim and Taewhan Kim
    Design and Utilization of Multi-skewed Multi-bit Flip-flop Cells for Timing Optimization: Design and Technology Co-optimization Approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (accepted).
  2. Kyungjoon Chang and Taewhan Kim
    Pre-route Timing Prediction and Optimization with Graph Neural Network Models
    Integration, the VLSI Journal Vol. 99, November 2024.
  3. Hyunbum Park, Kyeonghyeon Baek, Suwan Kim, Kyu-Myung Choi, and Taewhan Kim
    Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes with Consolidated Practical Applicability and Sustainability
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (accepted).
  4. Jooyeon Jeong and Taewhan Kim
    Placement Legalization for Heterogeneous Cells of Non-Integer Multiple-Heights
    Integration, the VLSI Journal March 2024.
  5. Jaehoon Ahn, Kyungjoon Chang, Kyu-Myung Choi, Taewhan Kim, and Heechun Park
    DTOC-P: Deep-learning-driven Timing Optimization using Commercial EDA Tool with Practicality Enhancement
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 43, No. 8, pp. 2493-2506, August 2024.
  6. Soomin Kim and Taewhan Kim
    Enhancing Design Qualities Utilizing Multi-bit Flip-flops: A Design and Technology Co-optimization Driven Approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 43, No. 5, pp. 1538-1551, May 2024.
  7. Kyeonghyeon Baek and Taewhan Kim
    CSyn-fp: Standard Cell Synthesis of Advanced Nodes with Simultaneous Transistor Folding and Placement
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 43, No. 2, pp. 627-640, February 2024.
  8. Eunsol Jeong, Taewhan Kim, and Heechun Park
    Eliminating Minimum Implant Area Violations with Design Quality Preservation
    IEEE Transactions on VLSI Systems Vol. 31, No. 5, pp. 611-621, May 2023.
  9. Sehyeon Chung and Taewhan Kim
    ECO Routing Based on Network Flow Method
    Integration, the VLSI Journal Vol. 86, pp. 1-8, September 2022.
  10. Jeongwoo Heo, Kwangok Jeong, Jungyun Choi, Taewhan Kim, and Kyumyung Choi
    Hardware Performance Monitoring Methodology for Circuits at Near-Threshold Computing and Advanced Technology Nodes: From Design to Post-Silicon
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 41, No. 6, pp. 1929-1942, June 2022.
  11. Jongsung Kang and Taewhan Kim
    Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks
    Journal of Computing Science and Engineering Vol. 161, No. 2, pp. 79-87, June 2022.
  12. Byungmin Ahn and Taewhan Kim
    Deeper Pruning without Accuracy Loss in Deep Neural Networks: Signed-digit Representation-based Approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 41, No. 3, pp. 656-668, March 2022.
  13. Heechun Park and Taewhan Kim
    Speeding-up Neuromorphic Computation for Neural Networks: Structure Optimization Approach
    Integration, the VLSI Journal Vol. 82, pp. 104-114, Jan. 2022.
  14. Jeongwoo Heo and Taewhan Kim
    Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
    IEEE Transactions on VLSI Systems Vol. 29, No. 7, pp. 1437-1450, July 2021.
  15. Gyounghwan Hyun and Taewhan Kim
    Allocation of Multi-Bit Retention Flip-flops for Power Gated Circuits: Algorithm – Design Unified Approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40, No. 5, pp. 892-903, May 2021.
  16. Changho Han and Taewhan Kim
    Synthesis of Representative Critical Path Circuits Considering BEOL Variations for Deep Sub-micron Circuits
    Integration, the VLSI Journal Vol. 78, pp. 1-10 May, 2021.
  17. Taehwan Kim, Heechun Park, and Taewhan Kim
    Allocation of Always-On State Retention Storage for Power Gated Circuits – Steady State Driven Approach
    IEEE Transactions on VLSI Systems Vol 29, No. 3, pp. 499-511, March 2021.
  18. Byungmin Ahn and Taewhan Kim
    Algorithm for Efficient Extraction of Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks
    Journal of Circuits, Systems, and Computers Vol. 30, No. 09, 2021.
  19. Taehwan Kim, Kwangok Jeong, Jungyun Choi, Taewhan Kim, and Kyumyung Choi
    SRAM On-chip Monitoring Methodology for High Yield and Energy Ecient Memory Operation at Near Threshold Voltage
    Integration, the VLSI Journal Vol. 74, pp. 81-92, September 2020.
  20. Jongsung Kang and Taewhan Kim
    PV-MAC: Multiply-and-Accumulate Unit Structure Exploiting Precision Variability in On-Device Convolutional Neural Networks
    Integration, the VLSI Journal Vol. 71, pp. 76-85, March 2020.
  21. Kyeongrok Jo, Seyong Ahn, Jungho Do, Taejoong Song, Taewhan Kim, and Kyumyung Choi
    Design Rule Evaluation Framework using Automatic Cell Layout Generator for Design Technology Co-Optimization
    IEEE Transactions on VLSI Systems Vol. 27, No. 8, pp. 1933-1946, August 2019.
  22. Heechun Park and Taewhan Kim
    Hybrid Asynchronous Circuit Generation Amenable to Conventional EDA Flow
    Integration, the VLSI Journal Vol. 64, pp. 29-39, 2019.
  23. Youngchan Kim and Taewhan Kim
    Synthesis and Exploration of Clock Spines
    IET Computers & Digital Techniques Vol. 12, No. 8, September 2018.
  24. Jeongwoo Heo and Taewhan Kim
    Circuit Timing Analysis and Optimization under Flexible Flip-flop Timing Model
    Journal of Semiconductor Technology and Science Vol. 7, No. 6, pp. 862-877, December 2017.
  25. Hyoungseok Moon and Taewhan Kim
    Loosely Coupled Multi-bit Flip-flop Allocation for Power Reduction
    Integration, the VLSI Journal, Vol. 58, pp. 125-133, June 2017.
  26. Deokjin Joo and Taewhan Kim
    Clock Buffer Polarity Assignment Under Useful Skew Constraints
    Integration, the VLSI Journal, Vol. 57, No. C, pp. 52-61, March 2017.
  27. Joohan Kim and Taewhan Kim
    Boundary Optimization of Buffered Clock Trees for Low Power
    Integration, the VLSI Journal, Vol. 56, No. C, pp. 86-95, January 2017.
  28. Juyeon Kim and Taewhan Kim
    Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 4, pp. 641-654, April 2017.
  29. Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, and Taewhan Kim
    Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage / Frequency Scaling
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35. No. 12, pp. 2068-2081, December, 2016.
  30. Hyoungjun Jeon and Taewhan Kim
    Gray-level Context-Driven Histogram Equalization
    IET Image Processing, Vol. 10, No. 5, pp. 349-358, May 2016.
  31. Juyeon Kim, Deokjin Joo, and Taewhan Kim
    Optimal Utilization of Adjustable Delay Clock Buffers for Timing Correction in Designs with Multiple Power Modes
    Integration, the VLSI Journal, Vol. 52, No. 1, pp. 91-101, January 2016.
  32. Hyoungjung Seo and Taewhan Kim
    Post Silicon Tuning Based on Flexible Flip-flop Timing
    Journal of Semiconductor Technology and Science, Vol. 16, No. 1, February 2016.
  33. Lu Cai and Taewhan Kim
    Context-Driven Hybrid Image Inpainting
    IET Image Processing, Vol. 9, No. 10, pp. 866-873, October 2015.
  34. Heechun Park and Taewhan Kim
    Synthesis of TSV Fault-Tolerant 3D Clock Trees
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 2, pp. 266-279, February 2015.
  35. Minseok Kang and Taewhan Kim
    Integrated Resource Allocation and Binding in Clock Mesh Synthesis
    ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 3, pp. 30:1-30:28, June 2014.
  36. Sangdo Park and Taewhan Kim
    Edge Layer Embedding Algorithm for Mitigating On-Package Variation in 3D Clock Tree Synthesis
    Integration, the VLSI Journal, Vol. 47, No. 4, pp. 476-486, September 2014.
  37. Byunghyun Lee and Taewhan Kim
    Algorithms for TSV Resource Sharing and Optimization in Designing 3D Stacked ICs
    Integration, the VLSI Journal, Vol. 47, No. 2, pp. 184-194, March 2014.
  38. Deokjin Joo and Taewhan Kim
    A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 3, pp. 423-436, March 2014.
  39. Kyoung-Hwan Lim, Deokjin Joo, and Taewhan Kim
    An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 3, pp. 392-405, March 2013.
  40. Tak-Yung Kim and Taewhan Kim
    Resource Allocation and Design Techniques of Pre-bond Testable 3D Clock Tree
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 138-151, January 2013.
  41. Jongyoon Jung and Taewhan Kim
    Statistical Viability Analysis for Detecting False Paths under Delay Variation
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 111-123, January 2013.
  42. Deokjin Joo, Minseok Kang, and Taewhan Kim
    Design Methodologies for Reliable Clock Networks
    Journal of Computing Science and Engineering, Vol. 6, No. 4, pp. 257-266, December 2012.
  43. Hyoungjung Seo, Jaewon Seo, and Taewhan Kim
    Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling
    The Computer Journal, Vol. 55, No. 11, pp. 1367-1382, November 2012.
  44. Jongyoon Jung and Taewhan Kim
    Variation Aware False Path Analysis Based on Statistical Dynamic Timing Analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.31, No.11, pp. 1684-1697, November 2012.
  45. Yonghwan Kim, Sanghoon Kwak, and Taewhan Kim
    Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
    ACM Transactions on Design Automation of Electronic Systems, Vol. 17, No. 4, pp. 43:1-43:29, October 2012.
  46. Tak-Yung Kim and Taewhan Kim
    Post Silicon Management of On-Package Variation Induced 3D Clock Skew
    Journal of Semiconductor Technology and Science, Vol. 12, No. 2, pp. 139-149, June 2012.
  47. Taewhan Kim
    Power Saving by Task-level Dynamic Voltage Scaling – A Theoretical Aspect in
    Book Chapter of Handbook of Energy-Aware and Green Computing, Chapman & Hall/CRC Computer & Information Science Series, Vol. 1, Edited by I. Ahmad and S. Ranka, January 2012.
  48. Tak-Yung Kim and Taewhan Kim
    Clock Tree Synthesis for TSV based 3D IC Designs
    ACM Transactions on Design Automation of Electronic Systems, Vol. 16, No. 4, pp. 48:1-48:21, October 2011.
  49. Yongho Lee, Deog-Kyoon Jeong, and Taewhan Kim
    Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits
    IEEE Transactions on VLSI Systems, Vol. 19, No. 3, pp. 494-498, March 2011.
  50. Yongho Lee and Taewhan Kim
    State Encoding Algorithm for Peak Current Minimization
    IET Computers & Digital Techniques, Vol. 5, No. 2, pp. 113-122, March 2011.
  51. Jongyoon Jung and Taewhan Kim
    Scheduling and Resource Binding Algorithm Considering Timing Variation
    IEEE Transactions on VLSI Systems, Vol. 19, No. 2, pp. 205-216, February 2011.
  52. Hochang Jang, Deokjin Joo, and Taewhan Kim
    Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 1, pp. 96-109, January 2011.
  53. Haneul Chon and Taewhan Kim
    Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC
    The Computer Journal, /Vol. 53, No. 7, pp. 883-894, September 2010.
  54. Taewhan Kim
    Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results
    Journal of Computing Science and Engineering, Vol. 4, No. 3, pp. 189-206, September 2010.
  55. Seungwhun Paik, Insup Shin, Taewhan Kim, and Youngsoo Shin
    HLS-l: A High-level Synthesis Framework for Latch-based Architectures
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, pp. 657-670, May 2010.
  56. Byunghyun Lee, Ki-seok Chung, Bontae Koo, Nak-woong Eum, and Taewhan Kim
    Thermal Sensor Allocation and Placement for Reconfigurable Systems
    ACM Transactions on Design Automation of Electronic Systems, Vol. 14, No. 4, August 2009.
  57. Pilok Lim, Ki-seok Chung, and Taewhan Kim
    Thermal-Aware High-level Synthesis Based on Network Flow Method
    Journal of Circuits, Systems and Computers, Vol. 18, No. 5, pp. 965-984, 2009.
  58. Kyung-Hwan Lim, YongHwan Kim, and Taewhan Kim
    Interconnect and Communication Synthesis for Distributed Register-File Micro-architecture
    IET Computers & Digital Techniques, Vol.3, No.2, pp. 162-174, March 2009.
  59. Benjamin Carrion Schafer and Taewhan Kim
    Autonomous Temperature Control Technique in VLSI Circuits Through Logic Replication
    IET Computers & Digital Techniques, Vol.3, No.1, pp. 62-71, January 2009.
  60. Benjamin Carrion Schafer and Taewhan Kim
    Hotspots Elimination and Temperature Flattening in VLSI Circuits
    IEEE Transactions on VLSI Systems, Vol. 16, No. 11, pp. 1475-1487, November 2008
  61. Yunheung Paek, Minook Ahn, Doosan Cho, and Taewhan Kim
    Efficient Embedded Code Generation with Multiple Load/Store Instructions
    Software-Practice & Experience, Vol. 37, No. 11, pp. 1133-1159, September 2007.
  62. Yongseok Choi, Naehyuck Chang and Taewhan Kim
    DC-DC Converter-Aware Power Management for Low-Power Embedded Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 8, pp. 1367-1381, 2007.
  63. Taewhan Kim and Jungeun Kim
    Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory Access Optimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 1, pp. 142-151, January 2007.
  64. Jong-U Shin and Taewhan Kim
    Technique for Transition Energy-Aware Dynamic Voltage Assignment
    IEEE Transactions on Integrated Circuits and Systems II, Vol. 53, No. 9, pp. 956-960, September 2006.
  65. Junhyung Um and Taewhan Kim
    Resource Sharing Combined with Layout Effects in High-Level Synthesis
    Journal of VLSI Signal Processing, Vol. 44, No. 3, pp. 231-243, September 2006.
  66. Young-Jun Kim and Taewhan Kim
    A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications
    Journal of VLSI Signal Processing, Vol. 44, No. 3, pp. 269-283, September 2006.
  67. Yoonseo Choi and Taewhan Kim
    Memory Access Driven Storage Assignment for Variables in Embedded System Design
    Journal of Circuits, Systems and Computers, Vol. 15, No. 2, pp. 145-168, April 2006.
  68. Chun-Gi Lyuh and Taewhan Kim
    Low Power Bus Encoding with Crosstalk Delay Elimination
    IET Computers & Digital Techniques, Vol. 153, No. 2, pp. 93-100, March 2006.
  69. Chun-Gi Lyuh and Taewhan Kim
    Memory Access Scheduling and Binding Considering Energy Minimization in Multi-Bank Memory Systems: An Integrated Approach
    IET Computers & Digital Techniques, Vol. 153, No. 1, pp. 59-68, January 2006.
  70. Jaewon Seo, Taewhan Kim and Joonwon Lee
    Optimal Intra-Task Dynamic Voltage Scaling and Its Practical Extensions
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 1, pp. 47-57, January 2006.
  71. Woo-Cheol Kwon and Taewhan Kim
    Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors
    ACM Transactions on Embedded Computing Systems, Vol. 4, No. 1, pp. 211-230, February 2005.
  72. Yoonseo Choi, Taewhan Kim, and Hwansoo Han
    Memory Layout Techniques for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 2, pp. 278-287, February 2005.
  73. Keoncheol Shin and Taewhan Kim
    Tight Integration of Timing-Driven Synthesis and Placement of Parallel Multiplier Circuits
    IEEE Transactions on VLSI Systems, Vol. 12, No. 7, pp. 766-775, July 2004.
  74. Nak-Woong Eum, Taewhan Kim, and Chong-Min Kyung
    CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
    IEEE Transactions on Computers, Vol. 53, No. 7, pp. 829-842, July 2004.
  75. Keoncheol Shin and Taewhan Kim
    Leakage Power Minimization in Arithmetic Circuits
    IEE Electronics Letters, Vol. 40, No. 7, pp. 415-417, April 2004.
  76. Chun-Gi Lyuh, Taewhan Kim and Ki-Wook Kim
    Coupling-Aware High-Level Interconnect Synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 1, pp. 157-164, January 2004.
  77. Junhynung Um and Taewhan Kim
    Synthesis of Arithmetic Circuits Considering Layout Effects
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 11, pp. 1487-1503, November 2003.
  78. Jaewon Seo, Taewhan Kim, and Preeti R. Panda
    Memory Allocation and Mapping in High-level Synthesis: An Integrated Approach
    IEEE Transactions on VLSI Systems, Vol. 11, No. 5, pp. 928-938, October 2003.
  79. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu and Sung-Mo Kang
    Coupling Delay Optimization by Temporal Decorelation using Dual Threshold Voltage Technique
    IEEE Transactions on VLSI Systems, Vol. 11, No. 5, pp. 879-887, October 2003.
  80. Yoonseo Choi and Taewhan Kim
    Address Assignment in DSP Code Generation – An Integrated Approach
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 22, No. 8, pp. 976-984, August 2003.
  81. Chun-Gi Lyuh and Taewhan Kim
    High-level Synthesis for Low-Power Based on Network Flow Method
    IEEE Transactions on VLSI Systems, Vol. 11, No. 3, pp. 364-375, June 2003.
  82. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, and Sung-Mo Kang
    Minimum Delay Optimization for Domino Logic Circuits: A Coupling-Aware Approach
    ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 2, pp. 203-213, April 2003.
  83. Sungpack Hong and Taewhan Kim
    Bus Optimization for Low Power in High-level Synthesis
    Journal of Circuits, Systems and Computers, Vol. 12, No. 1, pp. 1-16, Feb. 2003.
  84. Ki-Seok Chung, Rajesh Gupta, Taewhan Kim and C. L. Liu
    Synthesis and Optimization of Combinational Interface Circuits
    Journal of VLSI Signal Processing, Vol. 31, No. 2, pp. 243-261, July 2002.
  85. Yoonseo Choi and Taewhan Kim
    Binding Algorithm for Power Optimization Based on Network Flow Method
    Journal of Circuits, Systems and Computers, Vol. 11, No. 3, pp. 259-272, June 2002.
  86. Ki-Seok Chung, Taewhan Kim, and C. L. Liu
    A Complete Model for Glitch Analysis in Logic Circuits
    Journal of Circuits, Systems and Computers, Vol. 11, No. 2, pp. 137-154, Apr. 2002.
  87. Ki-Wook Kim, Taewhan Kim, Ting-Ting Hwang, C. L. Liu, and Sung-Mo Kang
    Logic Transformation for Low Power Synthesis
    ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 2, pp. 265-283, Apr. 2002.
  88. Ki-Wook Kim, Taewhan Kim, C. L. Liu, and Sung-Mo Kang
    Domino Logic Synthesis based on Implication Graph for Set of Mandatory Assignments
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 21, No. 2, pp. 232-240, Feb. 2002.
  89. Priyadarsan Patra, Unni Narayanan, and Taewhan Kim
    Phase Assignment for the Synthesis of Low Power Domino Circuits
    Electronics Letter, Vol. 37, No. 13, pp. 814-816, June 2001.
  90. Ki-Wook Kim, Seoong-Ook Jung, Taewhan Kim and Sung-Mo Kang
    Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits.
    Eletronics Letter, Vol.37, No.13, pp. 813-814, June 2001.
  91. Junhyung Um and Taewhan Kim
    An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.
    IEEE Transactions on Computers, Vol.50, No.3, pp. 215-233, March 2001.
  92. Ki-Seok Chung, Taewhan Kim and C.L.Liu
    G-vector: A New Model for Glitch Analysis in Logic Circuits.
    Journal of VLSI Signal Processing, Vol.27, No.3, pp. 235-252, March 2001.
  93. Sungpack Hong, Unni NArayanan,Ki-Seok Chung and Taewhan Kim
    Decompostion of Bus-invert Coding for Low-Power I/O
    Journal of Circuits, System and computers, Vol.10, No.1-2, pp.101-111, 2000.
  94. Youngtae Kim and Taewhan
    Accurate Exploration of Timing and Area Trade-offs in Arithmetic Optimization using Carry-Save-Adders
    Journal of Circuits, Systems and Computers, Vol. 10, No. 5 & 6, pp. 279-292, October & December 2000.
  95. Chaeryung Park, Taewhan Kim, and C. L. Liu
    An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization
    VLSI Design, Vol. 11, No. 4, pp. 381-396, 2000.
  96. Ki-Seok Chung, Taewhan Kim, and C. L. Liu
    Power Optimization of Multi-Level Logic Circuits Utilizing Circuit Symmetries
    International Journal of Electronics, Vol. 87, No. 7, pp. 841-852, July 2000.
  97. Taewhan Kim and Junhyung Um
    A Practical Approach to the Synthesis of Arithmetic Circuits using Carry-Save-Adders
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 19, No. 5, pp. 615-624, May 2000.
  98. Junhyung Um and Taewhan Kim
    Optimal Bit-level Arithmetic Optimization for High-Speed Circuits
    Electronics Letter, Vol. 36, No. 5, pp. 405-407, March 2000.
  99. Taewhan Kim, Ki-Seok Chung, and C. L. Liu
    A Stepwise Refinement Synthesis of Digital Systems for Testability Enhancement
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E82-A, No. 6, pp. 1070-1081, June 1999.
  100. Taewhan Kim, William Jao, and Steve Tjiang
    Circuit Optimization using Carry-Save-Adder Cells
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 17, No. 10, pp. 974-984, October 1998.
  101. Chaeryung Park, Taewhan Kim, and C. L. Liu
    Register Allocation – Hierarchical Reduction Approach
    Journal of VLSI Signal Processing, Vol. 19, No. 3, pp. 269-289, August 1998.
  102. Taewhan Kim and C. L. Liu
    An Integrated Algorithm for Incremental Data Path Synthesis
    Journal of VLSI Signal Processing, Vol. 12, No. 3, pp. 265-285, June 1996.
  103. Taewhan Kim and C. L. Liu
    A New Approach to the Multiport Memory Allocation Problem in Data Path Synthesis
    the VLSI Journal, INTEGRATION, Vol. 19, No. 3, pp. 133-160, 1995.
  104. Hideroni Nakazato, Jane W. S. Liu, and Taewhan Kim
    A Scheduling Strategy for Tasks with Precedence and Conditional Execution
    Transactions of Information Processing Society of Japan, Vol. 36, No. 9, pp. 2161-2174, September 1995.
  105. Taewhan Kim, Noritake Yonezawa, Jane W. S. Liu, and C. L. Liu
    A Scheduling Algorithm for Conditional Resource Sharing – A Hierarchical Reduction Approach
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 13, No. 4, pp. 425-438, April 1994.

Domestic Journals

  1. 김탁영, 김태환
    Physical Design for 3D Integrated Circuits
    대한전자공학회지 (The Magazine of IEEK), Vol. 36, No. 9, pp. 969-979, September 2009.
  2. 김영준, 김태환
    멀티모드 멀티태스크 임베디드 어플리케이션을 위한 HW/SW 분할 기법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 34, No. 7.8, pp. 337-347, August 2007.
  3. 최윤서, 김태환
    임베디드 시스템 설계에서 효율적인 메모리 접근을 고려한 변수 저장 방법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 32, No. 1.2, pp. 85-94, February 2005.
  4. 정기석, 김태환
    회로의 대칭성을 이용한 다단계 논리회로에서의 전력 소모 최소화 기법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 30, No. 9.10, pp. 504-511, October 2003.
  5. 서재원, 김태환, 정기석
    분산된 VLIW 구조에서의 최대 전력 최소화 방법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 30, No. 5.6, pp. 258-264, June 2003.
  6. 여준기, 김태환
    저전력과 크로스톡 지연 제거를 위한 버스 인코딩
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 29, No. 11.12, pp. 680-686, December 2002.
  7. 정기석, 김태환
    내장형 시스템 설계: 개론
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 20, No. 7, pp. 5-13, July 2002.
  8. 김태환, 정기석
    개선된 테스트 용이화를 위한 점진적 개선 방식의 데이터 경로 합성 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 29, No. 5.6, pp. 361-368, June 2002.
  9. 김태환, 엄준형
    캐리-세이브 가산기에 기초한 연산 하드웨어 최적화를 위한 실질적 합성 기법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 28, No. 9.10, pp. 520-529, October 2001.
  10. 김태환
    조건부 분기를 가진 데이터-흐름 그래프 스케줄링 알고리즘:변형을 통한 방법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 28, No. 1-2, pp. 103-109, February 2001.
  11. 홍성백, 김태환
    저전력을 위한 버스-인버트 코딩 분할 기법
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 28, No. 1-2, pp. 52-57, February 2001.
  12. 김태환
    네트워크-플로우 방법을 기반한 통합적 데이터-경로 합성 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 27, No. 12, pp. 981-987, December 2000.
  13. 김태환, 홍성백
    데이터 경로 합성에서의 연결선 최적화를 위한 다중포트 메모리 할당 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 27, No. 9, pp. 816-823, September 2000.
  14. 박채령, 김영태, 김태환
    상위 단계에서의 효율적인 저전력 데이터-경로 합성 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 27, No. 2, pp. 227-233, February 2000.
  15. 엄준형, 김태환
    회로 최적화를 위한 캐리-세이브 가산기 할당 알고리즘
    정보 과학회 컴퓨터 이론 연구회지 (SIGTCS), Vol. 10, No. 2, pp. 2-19, December 1999.
  16. 엄준형, 김태환
    캐리-세이브 가산기를 이용한 연산 최적화 알고리즘
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 26, No. 12, pp. 1539-1547, December 1999.
  17. 김태환, 엄준형
    VLSI 설계에서 캐리-세이브 가산기를 이용한 설계블럭들 간의 최적화
    정보 과학회 논문지 (KISS): Computer Systems and Theory, Vol. 26, No. 5, pp. 620-626, May 1999.

International Conferences

  1. Ensol Jeong, Taewhan Kim, and Heechun Park
    PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation
    IEEE/ACM Asis and South-Pacific Design Automation Conference (ASP-DAC), January 2025
  2. Sehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, and Taewhan Kim
    Optimal Layout Synthesis of Multi-row Standard Cells for Advanced Technology Nodes
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), October 2024
  3. Jayoung Yang and Taewhan Kim
    Improving Timing Quality Through Net Topology Optimization in Global Routing
    IEEE International System-on-Chip Conference (SOCC), September 2024
  4. Yeongyeong Shin and Taewhan Kim
    Design and Allocation of Multi-Bit Flip-Flop Cells Amenable to Placement Legalization in Physical Design
    IEEE International System-on-Chip Conference (SOCC), September 2024
  5. Taewhan Kim
    Recent Research in Design and Technology Co-Optimization with Multi-Bit Flip-Flops
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2024
  6. Suwan Kim and Taewhan Kim
    Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology
    IEEE/ACM Design Automation Conference (DAC), June 2024
  7. Jooyeon Jeong and Taewhan Kim
    Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization
    IEEE/ACM Design Automation Conference (DAC), June 2024
  8. Hwapyong Kim and Taewhan Kim
    Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing
    IEEE International symposium on Circuits and Systems (ISCAS), May 2024
  9. Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, and Taewhan Kim
    Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes
    IEEE/ACM Design, Automation and Test in Europe Conference (DATE), March 2024
  10. Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, and Taewhan Kim
    BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost
    IEEE/ACM Design, Automation and Test in Europe Conference (DATE), March 2024
  11. Suwan Kim, Hyunbum Park, Kyeonghyeon Baek, Kyu-Myung Choi, and Taewhan Kim
    Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model
    ACM International Symposium on Physical Design (ISPD), March 2024
  12. Suwan Kim and Taewhan Kim
    Design and Technology Co-optimization for Useful Skew Scheduling on Multi-bit Flip-flops
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2023
  13. Jinmyoung Kim and Taewhan Kim
    Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips
    IEEE International SoC Design Conference (ISOCC), October 2023
  14. Chaehyun Kim and Taewhan Kim
    Maximizing Power Saving Through State-Driven Clock Gating
    IEEE International SoC Design Conference (ISOCC), October 2023
  15. Ilseon Ha and Taewhan Kim
    Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow
    IEEE International SoC Design Conference (ISOCC), October 2023
  16. Kihwan Jeon and Taewhan Kim
    Fast Refinement on Placement Legalization for Designs with Mixed-Height Cells
    IEEE International SoC Design Conference (ISOCC), October 2023
  17. Jaewan Yang and Taewhan Kim
    Debanking Techniques on Multi-Bit Flip-Flops for Reinforcing Useful Clock Skew Scheduling
    IEEE International System-on-Chip Conference (SOCC), September 2023
  18. Taewhan Kim
    Challenges on Design and Technology Co-optimization: Design Automation Perspective
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2023
  19. Doyeon Won, Soomin Kim, and Taewhan Kim
    Machine Learning Driven Synthesis of Clock Gating
    IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2023
  20. Hwapyong Kim and Taewhan Kim
    Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool
    ACM Great Lakes Symposium on VLSI (GLSVLSI), June 2023
  21. Sora Park and Taewhan Kim
    Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating
    IEEE International symposium on Circuits and Systems (ISCAS), May 2023
  22. Kyungjoon Chang, Heechun Park, Jaehoon Ahn, Kyu-Myung Choi, and Taewhan Kim
    DTOC: integrating Deep-learning driven Timing Optimization into state-of-the-art Commercial EDA tool
    IEEE/ACM Design, Automation and Test in Europe Conference (DATE), April 2023
  23. Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, and Taewhan Kim
    Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility
    IEEE/ACM Design, Automation and Test in Europe Conference (DATE), April 2023
  24. Jaehoon Ahn and Taewhan Kim
    Neural Network Model for Detour Net Prediction
    ACM/IEEE International Workshop on System-level Interconnect Pathfinding (SLIP), November 2022
  25. Kyungjoon Chang and Taewhan Kim
    Analysis of Impacting Multi-stack Standard Cells on Chip Implementation
    IEEE International SoC Design Conference (ISOCC), October 2022
  26. Soomin Kim and Taewhan Kim
    Design and Technology Co-optimization Utilizing Multi-bit Flip-flop Cells
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), October 2022
  27. Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, and Taewhan Kim
    Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction using Graph Neural Network and U-Net
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), October 2022
  28. Suwan Kim, Sehyeon Chung, Taewhan Kim, and Heechun Park
    Tightly Linking 3D via Allocation towards Routing Optimization for Monolithic 3D ICs
    IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2022
  29. Sehyeon Chung, Jooyeon Jeong, and Taewhan Kim
    Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis
    IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2022
  30. Doyeon Won and Taewhan Kim
    Improving Pin Accessibility of Standard Cells Through Pin Depopulation
    IEEE International symposium on Circuits and Systems (ISCAS), May 2022
  31. Sora Park and Taewhan Kim
    Selective Clock Gating Based on Comprehensive Power Saving Analysis
    IEEE International symposium on Circuits and Systems (ISCAS), May 2022
  32. Soomin Kim and Taewhan Kim
    Optimizing Timing in Placement Through I/O Signal Flipping on Multi-Bit Flip-Flops
    IEEE International symposium on Circuits and Systems (ISCAS), May 2022
  33. Suwan Kim and Taewhan Kim
    Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model
    IEEE/ACM Design, Automation and Test in Europe Conference (DATE), March 2022
  34. Eunsol Jeong, Heechun Park, and Taewhan Kim
    A Systematic Removal of Minimum Implant Area Violations under Timing Constraint
    IEEE/ACM Design, Automation and Test in Europe Conference (DATE), March 2022
  35. Kyeonghyeon Baek and Taewhan Kim
    Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis
    IEEE International Conference on Computer-Aided Design (ICCAD), Novermber 2021
  36. Kyeongrok Jo and Taewhan Kim
    Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis
    IEEE International Conference on Computer Design (ICCD), October 2021
  37. Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, and Taewhan Kim
    Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology
    IEEE International SoC Design Conference (ISOCC), October 2021
  38. Jaejoon Yoon, Sehyeon Chung, and Taewhan Kim
    Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops
    IEEE International SoC Design Conference (ISOCC), October 2021
  39. Suwan Kim and Taewhan Kim
    Practical Approach to Cell Replacement for Resolving Pin Inaccessibility
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2021
  40. Jooyeon Jeong and Taewhan Kim
    Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2021
  41. Eunsol Jeong, Heechun Park, Jooyeon Jeong, and Taewhan Kim
    Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2021
  42. Kyungjoon Chang and Taewhan Kim
    Chip Implementation using Standard Cells with Intensive Use of Middle-of-Line Layers
    International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2021
  43. Soomin Kim and Taewhan Kim
    Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits
    IEEE International Symposium on Quality Electronic Design (ISQED), April 2021
  44. Jongsung Kang and Taewhan Kim
    Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks
    IEEE/ACM Design, Automation and Test in Europe Conference (DATE), March 2021
  45. Suwan Kim, Kyeongrok Jo, and Taewhan Kim
    Boosting Pin Accessibility Through Cell Layout Topology Diversification
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2021
  46. Taehwan Kim, Gyounghwan Hyun, and Taewhan Kim
    Steady State Driven Power Gating for Lightening Always-on State Retention Storage
    IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2020 (Best Paper Nomination)
  47. Byungmin Ahn and Taewhan Kim
    Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks
    IEEE/ACM Design, Automation and Test in Europe Conference (DATE), March 2020 (Best Paper Nomination)
  48. Jeongwoo Heo and Taewhan Kim
    Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2020
  49. Jeongwoo Heo, Taewhan Kim, and Kyumyung Choi
    Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2020
  50. Gyounghwan Hyun and Taewhan Kim
    Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2019
  51. Gyounghwan Hyun and Taewhan Kim
    Flip-flop State Driven Clock Gating: Concept, Design, and Methodology
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2019
  52. Taehwan Kim, Kwang Ok Jeong, Taewhan Kim, and Kyumyung Choi
    SRAM On-chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage
    IEEE Symposium on VLSI (ISVLSI), July 2019
  53. Byungmin Ahn and Taewhan Kim
    Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks
    IEEE International System-on-Chip Conference (SOCC), September 2018
  54. Giyoung Yang and Taewhan Kim
    Design and Algorithm for Clock Gating and Flip-flops Co-optimization
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2018
  55. Juyeon Kim and Taewhan Kim
    Energy-Optimal Dynamic Voltage Scaling in Multicore Platforms with Reconfigurable Power Distribution Network
    IEEE International Symposium on Quality Electronic Design (ISQED), March 2018
  56. Joohan Kim and Taewhan Kim
    Clock Buffer and Flip-flop Co-optimization for Reducing Peak Current Noise
    IEEE International Symposium on Quality Electronic Design (ISQED), March 2018
  57. Heechun Park and Taewhan Kim
    Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Networks
    IEEE/ACM Design, Automation and Test in Europe (DATE), March 2018
  58. Kyeongrok Jo, Seyong Ahn, Taewhan Kim, and Kyumyung Choi
    Cohesive Techniques for Cell Layout Optimization Supporting 2D Metal-1 Routing Completion
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018
  59. Dongyoun Yi and Taewhan Kim
    Switch Cell Optimization of Power-gated Modern System-on-Chips
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2017
  60. Hyoungjun Jeon and Taewhan Kim
    Community-Adaptive Link Prediction
    International Conference on Data Mining, Commnuications and Information Technology (DMCIT), May 2017
  61. Youngchan Kim and Taewhan Kim
    Algorithm for Synthesis and Exploration of Clock Spines
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2017 (Best Paper Nomination)
  62. Dongyoun Yi and Taewhan Kim
    Allocation of Multi-bit Flip-flops in Logic Synthesis
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2016
  63. Jeongwoo Heo and Taewhan Kim
    Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model
    IEEE Symposium on VLSI (ISVLSI), July 2016
  64. Heechun Park and Taewhan Kim
    Synthesizing Asynchronous Circuits Toward Practical Use
    IEEE Symposium on VLSI (ISVLSI), July 2016
  65. Hyoungseok Moon and Taewhan Kim
    Design and Allocation of Loosely Coupled Multi-bit Flip-flops for Power Reduction in Post-Placement Optimization
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2016
  66. Deokjin Joo and Taewhan Kim
    Clock Buffer Polarity Assignment Utilizing Useful Clock Skews for Power Noise Reduction
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2016
  67. Deokjin Joo and Taewhan Kim
    Managing Clock Skews in Clock Trees with Local Clock Skew Requirements Using Adjustable Delay Buffers
    IEEE International SoC Design Conference (ISOCC), November 2015
  68. Hyoungjung Seo, Juyeon Kim, Minseok Kang, and Taewhan Kim
    Synthesis for Power-Aware Clock Spines
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2015
  69. Hyoungjun Jeon and Taewhan Kim
    Globally Tunable Histogram Equalization for Image Enhancement
    International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2015
  70. Hyoungjung Seo, Jeongwoo Heo, and Taewhan Kim
    Clock Skew Optimization for Maximizing Time Margin by Utilizing Flexible Flip-Flop Timing
    IEEE International Symposium on Quality Electronic Design (ISQED), March 2015
  71. Seyong Ahn, Minseok Kang, Marios Papaefthymiou, and Taewhan Kim
    Synthesis of Resonant Clock Networks Supporting Dynamic Voltage / Frequency Scaling
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2015
  72. Juyeon Kim and Taewhan Kim
    Useful Clock Skew Scheduling using Adjustable Delay Buffers in Multi-Power Mode Designs
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2015 (Best Paper Nomination)
  73. Juyeon Kim and Taewhan Kim
    Energy-Optimal Algorithm for Dynamic Voltage Scaling with Non-Convex Power Functions
    IEEE International SoC Design Conference (ISOCC), November 2014
  74. Hyoungjung Seo, Jeongwoo Heo, and Taewhan Kim
    Fast Allocation of Post-Silicon Tunable Buffers to Mitigate Timing Variation
    IEEE International SoC Design Conference (ISOCC), November 2014
  75. Sangdo Park, Jeongwoo Heo, and Taewhan Kim
    Allocation and Optimization of Post-Silicon Tunable Buffers in TSV Based Heterogeneous 3D ICs
    IEEE International SoC Design Conference (ISOCC), November 2014
  76. Sangdo Park and Taewhan Kim
    Post-Silicon Tuning Aware Wafer Matching Algorithm for 3D Integration of ICs
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2014
  77. Myungwoo Lee and Taewhan Kim
    Fast Algorithm of Low Power Image Reformation of OLED Display
    International Conference on Digital Image Processing (ICDIP), April 2014
  78. Kitae Park, Geunho Kim and Taewhan Kim
    Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Desgns
    IEEE Design Automation & Test in Europe (DATE), March 2014
  79. Hyoungjung Seo and Taewhan Kim
    Post-Silicon Tunable Clock Buffer Allocation Based on Fast Chip Yield Computation
    IEEE International Symposium on Quality Electronic Design (ISQED), March 2014
  80. Seyong Ahn, Minseok Kang, and Taewhan Kim
    Power-Aware Inductor Analysis in Resonant Clock Networks
    IEEE International SOC Design Conference (ISOCC), November 2013
  81. Heechun Park and Taewhan Kim
    Fault Coverage and Resource Analysis for Diverse Structures of Clock TSV Fault-Tolerant Units in 3D ICs
    IEEE International SOC Design Conference (ISOCC), November 2013
  82. Heechun Park and Taewhan Kim
    Comprehensive Technique for Designing and Synthesizing TSV Fault-Tolerant 3D Clock Trees
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2013
  83. Sandeep Kumar Samal, Kiyoung Kim, Youngchan Kim, Taesung Kim, Hyuk-Jae Lee, Taewhan Kim and Sung Kyu Lim
    Ultra Low Power 2-tier 3D Stacked Sub-threshold H.264 Intra Frame Encoder
    IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2013
  84. Byunghyun Lee and Taewhan Kim
    High-level TSV Resource Sharing and Optimization for TSV Based 3D IC Designs
    IEEE International System-on-Chip Conference (SOCC), September 2013 (Best Paper Award)
  85. Juyeon Kim, Deokjin Joo, and Taewhan Kim
    An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem
    IEEE/ACM Design Automation Conference (DAC), June 2013
  86. Sangdo Park and Taewhan Kim
    Die Matching Algorithm for Enhancing Parametric Yield of 3D ICs
    IEEE International SOC Design Conference (ISOCC), pp. 143-146, November 2012
  87. ByungHyun Lee and Taewhan Kim
    TSV-Aware Hierarchical Floorplanning for 3D ICs
    International Conference on Electronics, Information, and Communication (ICEIC), pp. 207-208, February 2012
  88. Kiyoung Kim and Taewhan Kim
    Algorithm for Synthesizing Design Context-Aware Fast Carry-Skip Adders
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 795-800, January 2012
  89. Younghwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sando Park, Deokjin Joo, and Taewhan Kim
    Clock Design Techniques Considering Circuit Reliability
    IEEE International SOC Design Conference (ISOCC), pp. 142-145, November 2011
  90. Sangdo Park and Taewhan Kim
    Algorithm for Temperature-Aware Idle Time Distribution Considering Mode Transition Overhead
    IEEE International SOC Design Conference (ISOCC), pp. 381-384, November 2011
  91. Joohan Kim and Taewhan Kim
    A Fine-Grained Timing Driven Synthesis of Arithmetic Circuits
    IEEE International SOC Design Conference (ISOCC), pp. 80-83, November 2011
  92. Tak-Yung Kim and Taewhan Kim
    Clock Network Design Techniques for 3D ICs
    International Midwest Symposium on Circuits and Systems (MWSCAS), pp. August 2011
  93. Tak-Yung Kim and Taewhan Kim
    On-Package Variation and Body Biasing Analysis on 3D Clock Tree
    International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 199-202, June 2011
  94. Deokjin Joo and Taewhan Kim
    WaveMin: A Fine-Grained Clock Buffer Polarity Assignment Combined with Buffer Sizing
    IEEE/ACM Design Automation Conference (DAC), pp. 522-527, June 2011
  95. Kyoung-Hwan Lim and Taewhan Kim
    An Optimal Algorithm for Allocation, Placement, and Delay Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 503-508, January 2011
  96. Yongho Lee and Taewhan Kim
    A Fine-Grained Technique of NBTI-Aware Voltage Scaling and Body Biasing for Standard Cell Based Design
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 603-608, January 2011
  97. Danbee Park, Jungseob Lee, Nam Sung Kim, and Taewhan Kim
    Optimal Algorithm for Profile-Based Power Gating: A Compiler Technique for Reducing Leakage on Execution Units in Microprocessors
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 361-364, November 2010
  98. Pilok Lim and Taewhan Kim
    Thermal-Aware Resource Rebinding Algorithm for Timing Optimization in 3D IC Designs
    IEEE International SOC Design Conference (ISOCC), pp. 290-293, November 2010 (Best Paper Award)
  99. Tak-Yung Kim and Taewhan Kim
    Bounded Skew Clock Routing for 3D Stacked IC Designs: Enabling Trade-offs Between Power and Clock Skew
    IEEE International Green Computing Conference, pp. 525-532, August 2010
  100. Tak-Yung Kim and Taewhan Kim
    Clock Tree Synthesis with Pre-bond Testability for 3D Stacked IC Designs
    IEEE/ACM Design Automation Conference (DAC), pp. 723-728, June 2010
  101. Minseok Kang and Taewhan Kim
    Clock Buffer Polarity Assignment Considering the Effect of Delay Variations
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 69-74, March 2010
  102. Tak-Yung Kim and Taewhan Kim
    Clock Tree Embedding for 3D ICs
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 486-491, January 2010
  103. Yongho Lee and Taewhan Kim
    Technique for Controlling Power-Mode Transition Noise in Distributed Sleep Transistor Network
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 131-136, January 2010
  104. Yongho Lee, Kiyoung Choi, and Taewhan Kim
    SAT-Based State Encoding for Peak Current Minimization
    IEEE International SOC Design Conference (ISOCC), pp. 432-435, November 2009
  105. Jongyoon Jung and Taewhan Kim
    Timing Variation Aware High-Level Synthesis Considering Accurate Yield Computation
    IEEE International Conference on Computer Design (ICCD), October 2009
  106. Hochang Jang and Taewhan Kim
    Simultaneous Clock Buffer Sizing and Polarity Assignment for Power/Ground Noise Minimization
    IEEE/ACM Design Automation Conference (DAC), pp. 794-799, July 2009
  107. Haneul Chon and Taewhan Kim
    Timing Variation-Aware Task Scheduling and Binding for MPSoC
    IEEE Asia and South-Pacific Design Automation Conference (ASP-DAC), pp. 137-142, January 2009
  108. Jongyoon Jung and Taewhan Kim
    Timing Variation-Aware High-Level Synthesis: Current Results and Research Challenges
    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1004-1007, December 2008
  109. Yongho Lee, Deog-Kyoon Jeong, and Taewhan Kim
    Simultaneous Control of Power/Ground Current, Wakeup Time and Transistor Overhead in Power Gated Circuits
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 169-172, November 2008
  110. Yesin Ryu and Taewhan Kim
    Clock Buffer Polarity Assignment Combined with Clock Tree Generation for Power/Ground Noise Minimization
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.416-419, November 2008
  111. Eunjoo Choi, Changsik Shin, Taewhan Kim, and Youngsoo Shin,
    Power Gating-Aware High-level Synthesis
    IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 39-44, August 2008
  112. Sungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung Choi, Soo-Kwan Eo, and Taewhan Kim
    Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution
    IEEE/ACM Design Automation & Test in Europe (DATE), pp. 242-247, March 2008
  113. ByungHyun Lee and Taewhan Kim
    Optimal Allocation and Placement of Thermal Sensors for Reconfigurable Systems and Its Practical Extension
    IEEE Asia and South-Pacific Design Automation Conference (ASP-DAC), pp. 703-707, January 2008
  114. Jongyoon Jung and Taewhan Kim
    Timing Variation-Aware High-Level Synthesis
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 424-428, November 2007
  115. Benjamin Carrion Schafer, Yongho Lee, and Taewhan Kim
    Temperature-Aware Compilation for VLIW Processors
    IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 426-431, August 2007
  116. Kyoun-Hwan Lim, YongHwan Kim, and Taewhan Kim
    Interconnect and Communication Synthesis for Distributed-File Microarchitecture
    IEEE/ACM Design Automation Conference (DAC), pp. 765-770, June 2007
  117. Zhenmin Li and Taewhan Kim
    Address Code Optimization Exploiting Code Scheduling in DSP Applications
    IEEE International symposium on Circuits and Systems (ISCAS), pp. 1573-1576, May 2007
  118. Benjamin Carrion Schafer and Taewhan Kim
    Thermal-Aware Instruction Assignment for VLIW Processors
    The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11), Feb. 2007
  119. Pilok Lim and Taewhan Kim
    Thermal-Aware High-Level Synthesis Based on Network Flow Method
    ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 124-129, October 2006
  120. Taewhan Kim
    Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling
    IEEE International Conference on Embedded and Real-Time Computing Systems and Application (RTCSA), pp. 199-206, August 2006 (Invited)
  121. Youngjun Kim and Taewhan Kim
    HW/SW Partitioning Techniques for Multi-Mode Multi-Task Embedded Applications
    ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 25-30, April 2006
  122. Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, and Taewhan Kim
    A Systematic IP and Bus Subsystem Modeling for Platform Based System Design
    IEEE Design, Automation and Test in Europe (DATE), pp. 560-565, March 2006
  123. Junhyung Um, Woo-Cheol Kwon, Hoon-Sang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, and Taewhan Kim
    A Systematic Transaction-level Modeling and Verification
    Design & Verification Conference (DVCon), pp. 163-168, February 2006
  124. Jaewon Seo, Taewhan Kim, and Nikil D. Dutt
    Optimal Integration of Intra- and Inter task Dynamic Voltage Scaling for Hard Real-Time Applications
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 450-455, November 2005
  125. Jong-U Shin and Taewhan Kim
    Techniques for Transition Energy-Aware Dynamic Voltage Assignment
    International SOC Conference (ISOCC), October 2005
  126. Daegun Won and Taewhan Kim
    Improvement to the Leakage Power Minimization Techniques for Arithmetic Circuits
    International SOC Conference (ISOCC), October 2005
  127. Byungho Lee and Taewhan Kim,
    Code Compression Combined with Low-Power Encoding
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2005
  128. Shin Hong and Taewhan Kim,
    Address Code Generation Utilizing Memory Sharing in DSP Processors
    IEEE Midwest Symposium on Circuits and Systems (MWSCAS), August 2005
  129. Jungeun Kim and Taewhan Kim
    Memory Acces Optimization Through Combined Code Scheduling, Memory Allocation, and Array Binding in Embedded System Design
    IEEE/ACM Design Automation Conference (DAC), pp. 105-110, June 2005
  130. Yongseok Choi, Naehyuck Chang, and Taewhan Kim
    DC-DC Converte-Aware Power Management for Battery-Operated Embedded Systems
    IEEE/ACM Design Automation Conference (DAC), pp. 895-900, June 2005
  131. Doonguk Lee and Taewhan Kim
    High-level Synthesis using Carry-Save Adders
    International SOC Conference (ISOCC), October 2004
  132. Chun-Gi Lyuh and Taewhan Kim
    Memory Access Scheduling and Binding Considering Energy Minimization in Multi-Bank Memory Systems
    IEEE/ACM Design Automation Conference (DAC), pp. 81-86, June 2004
  133. Jaewon Seo, Taewhan Kim and Kiseok Chung
    Profile-based Optimal Intra-task Voltage Scheduling for Hard Real-Time Applications
    IEEE/ACM Design Automation Conference (DAC), pp. 87-92, June 2004
  134. Keoncheol Shin and Taewhan Kim
    Leakage Power Minimization for the Synthesis of Parallel Multiplier Circuits
    ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 166-169, April 2004
  135. Meeyoung Cha, Chun-Gi Lyuh and Taewhan Kim
    Resource-Constrained Low-Power Bus Encoding with Crosstalk Delay Elimination
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 835-838, January 2004
  136. Keoncheol Shin and Taewhan Kim
    An Integrated Approach to Timing-Driven Synthesis and Placement of Arithmetic Circuits
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 155-158, January 2004
  137. Yoonseo Choi and Taewhan Kim
    Memory Access Driven Storage Assignment for Variables in Embedded System Design
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 478-481, January 2004
  138. Junhyung Um and Taewhan Kim
    Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 197-200, November 2003
  139. Yoonseo Choi and Taewhan Kim
    Memory Layout Technique for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design
    IEEE/ACM Design Automation Conference (DAC), pp. 881-886, June 2003
  140. Woocheol Kwon and Taewhan Kim
    Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors
    IEEE/ACM Design Automation Conference (DAC), pp. 125-130, June 2003 (Best Paper Nomination)
  141. Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jeon and Taewhan Kim
    An Efficient Inverse Multiplier/Divider Architecture for Cryptography Systems
    IEEE International Symposium on Circuits and Systems (ISCAS), Vol. V pp. 149-152, May 2003
  142. Junhyung Um, Jae-Hoon Kim and Taewhan Kim
    Layout-Driven Resource Sharing in High-level Synthesis
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 609-613, November 2002
  143. Chungi Lyuh, Taewhan Kim and Ki-Wook Kim
    Coupling-Aware High-level Interconnect Synthesis for Low Power
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 614-619, November 2002
  144. Chungi Lyuh and Taewhan Kim
    Low Power Bus Encoding with Crosstalk Delay Elimination
    IEEE ASIC/SOC Conference (ASIC), pp. 389-393, September 2002
  145. Yoonseo Choi and Taewhan Kim
    Address Assignment Combined with Scheduling in DSP Code Generation
    IEEE/ACM Design Automation Conference (DAC), pp. 225-230, June 2002
  146. Jaewon Seo, Taewhan Kim and Preeti R. Panda
    An Integrated Algorithm for Memory Allocation and Assignment in High-level Synthesis
    IEEE/ACM Design Automation Conference (DAC), pp. 608-611, June 2002
  147. Junhyung Um and Taewhan Kim
    Layout-Aware Synthesis of Arithmetic Circuits
    IEEE/ACM Design Automation Conference (DAC), pp. 207-212, June 2002
  148. Narayanan Unni, Ki-Seok Chung and Taewhan Kim
    Enhanced Bus Invert Encoding for Low-Power
    IEEE International Symposium on Circuits and Systems (ISCAS), Vol. V, pp. 25-28, May 2002
  149. Jaewon Seo and Taewhan Kim
    Memory Exploration utilizing Scheduling Effects in High-level Synthesis
    IEEE International Symposium on Circuits and Systems (ISCAS), Vol. IV, pp. 73-76, May 2002
  150. Yoonseo Choi and Taewhan Kim
    An Efficient Low-Power Binding Algorithm in High-level Synthesis
    IEEE International Symposium on Circuits and Systems (ISCAS), Vol. IV, pp. 321-324, May 2002
  151. Yoonseo Choi and Taewhan Kim
    Address Code Optimization using Code Scheduling for Digital Signal Processors
    IEEE International Symposium on Circuits and Systems (ISCAS), Vol V, pp. 481-484, May 2002.
  152. Chungi Lyuh, Taewhan Kim, and C. L. Liu
    An Integrated Data Path Optimization for Low Power Based on Network Flow Method
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 553-559, Nov. 2001
  153. Nak-Woong Eum, Taewhan Kim, and Chong-Min Kyung
    A Router for Symmetrical FPGA Based on Exact Routing Density Evaluation
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 137-143, Nov. 2001
  154. Yoonseo Choi and Taewhan Kim
    An Efficient Binding Algorithm for Power Optimization based on Network Flow Method
    6th Korea-Japan Joint Workshop on Algorithms and Computation, pp. 9-14, June 2001
  155. Chungi Lyuh and Taewhan Kim
    Power Optimization in VLSI Design based on Efficient Network Flow Computations
    6th Korea-Japan Joint Workshop on Algorithms and Computation, pp. 3-8, June 2001
  156. Taewhan Kim, Ki-Seok Chung, and C. L. Liu
    A Static Estimation Technique of Power Sensitivity in Logic Circuits
    ACM/IEEE Design Automation Conference (DAC), pp. 215-219, June 2001
  157. Nak-Woong Eum, Taewhan Kim, and Chong-Min Kyung
    An Accurate Evaluation of Routing Density for Synnetrical FPGAs
    ACM Great LAkes Synposium on VLSI, March 2001.
  158. Youngtae Kim and Taewhan Kim
    An Accurate Design Exploration of Arithmetic Circuits using Carry-Save-Adder Cells
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2001.
  159. Sungpack Hong and Taewhan Kim
    Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
    IEEE International Conference on Computer-Aided Design (ICCAD), pp.312-317, November 2000.
  160. Gernot Koch, Taewhan Kim, and Reiner Genevriere
    A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
    IEEE International Conference on Computer-Aided Design (ICCAD), pp.33-38, November 2000.
  161. Ki-Seok Chung,Taewhan Kim, and C.L.Liu
    Complete Model for Glitch Analysis in Logic Circuit
    IEEE International ASIC/SOC Conference (ASIC), September 2000.
  162. Young-Tae Kim and Taewhan Kim
    An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization using Carry-Save Adder Cells
    IEEE MidWest Symposium on Circuits and Systems (MWSCAS), August 2000.
  163. Sungpack Hong, Unni Narayanan, Ki-Seok Chung, and Taewhan Kim
    Bus-Invert Coding for Low-Power I/O – A Decomposition Approach
    IEEE MidWest Symposium on Circuits and Systems (MWSCAS), August 2000.
  164. Gernot Koch, Taewhan Kim, and Reiner Genevriere
    A Verification of Memory Access Protocols in Behavioral Synthesis
    IEEE MidWest Symposium on Circuits and Systems (MWSCAS), August 2000.
  165. Ki-Seok Chung, Taewhan Kim, and C. L. Liu
    A Non-Zero Delay Model for Glitch Analysis in Logic Circuits
    IEEE MidWest Symposium on Circuits and Systems (MWSCAS), pp. 1244-1247, August 2000.
  166. Junhyung Um, Taewhan Kim, and C. L. Liu
    A Fine-Grained Arithmetic Optimization for High-Performance / Low-Power Data Path Synthesis
    ACM/IEEE Design Automation Conference (DAC), June 2000.
  167. Ki-Seok Chung, Taewhan Kim, and C. L. Liu
    Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications
    ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 156-161, March 2000.
  168. Taewhan Kim and Junhyung Um
    A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 313-316, January 2000.
  169. Junhyung Um, Taewhan Kim and C. L. Liu
    Optimal Allocation of Carry-Save-Adders in Arithmetic Optimization
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 410-413, November 1999.
  170. Junhyung Um and Taewhan Kim
    Wallace-Tree based Timing-Driven Synthesis of Arithmetic Circuits
    IEEE International Conference on VLSI and CAD (ICVC), pp. 89-94, October 1999.
  171. Junhyung Un and Taewhan Kim
    Utilization of Carry-Save Adders in Arithmetic Optimization
    IEEE International ASIC/SOC Conference (ASIC), pp. 173-177, September 1999.
  172. Ki-Seok Chung, Taewhan Kim, and C. L. Liu
    G-Vector: A New Model for Glitch Analysis
    IEEE International ASIC/SOC Conference (ASIC), pp. 159-162, September 1999.
  173. Chaeryung Park, Taewhan Kim, and C. L. Liu
    An Integrated Approach to Data Path Synthesis for Low Power
    IEEE International ASIC/SOC Conference (ASIC), pp. 125-129, September 1999.
  174. Chaeryung Park, Taewhan Kim, and C. L. Liu
    An Efficient Data Path Synthesis Algorithm for Behavioral-level Power Optimization
    IEEE International Symposium on Circuits and Systems (ISCAS), pp. I-294-I-297, May 1999.
  175. Taewhan Kim, William Jao, and Steve Tjiang
    Arithmetic Optimization using Carry-Save Adders
    ACM/IEEE Design Automation Conference (DAC), pp. 442-447, June 1998.
  176. Taewhan Kim and C. L. Liu
    An Integrated Data Path Synthesis Algorithm Based on Network Flow Method i
    IEEE Custom Integrated Circuits Conference (CICC), pp. 615-618, May 1995.
  177. Taewhan Kim, Ki-seok Chung, and C. L. Liu
    A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability
    IEEE European Design and Test Conference (EDAC), pp. 586-590, February 1994.
  178. Chaeryung Park, Taewhan Kim, and C. L. Liu
    Register Allocation for Dataflow Graphs with Conditional Branches and Loops
    IEEE European Design Automation Conference (EURO-DAC), pp. 586-590, September 1993.
  179. Taewhan Kim and C. L. Liu
    Utilization of Multiport Memories in Data Path Synthesis
    IEEE Design Automation Conference (DAC), pp. 298-302, June 1993.
  180. Taewhan Kim and Jane W. S. Liu, and C. L. Liu
    A Scheduling Algorithm for Conditional Resource Sharing
    IEEE International Conference on Computer Aided Design (ICCAD), pp. 84-87, November 1991.

Domestic Conferences

  1. 강종성, 허정우, 김태환
    이미지 특징점 추출 방법에 따른 Bag of Word 성능 비교
    대한전자공학회 하계학술대회, 2015년
  2. 서형중, 김태환
    3차원 집적 회로에서의 Power Delivery Network 구조 분석
    대한전자공학회 추계학술대회, pp. 35-38, 2012년
  3. 김영찬, 김태환
    클락 동기화를 위한 3-입력 Bang-Bang 위상검출기 설계
    대한전자공학회 추계학술대회, pp. 74-76, 2012년
  4. 박희천, 김태환
    Clock TSV Fault-Tolerant한 3차원 IC 설계를 위한 TSV 공유 일고리즘
    대한전자공학회 추계학술대회, pp. 111-114, 2012년
  5. 김주한, 김태환
    빠른 연산 회로 합성을 위한 셀사이징 기법
    대한전자공학회 추계학술대회, pp. 129-130, 2012년
  6. 임필옥, 김태환
    페이지 모드 메모리 접근 활용을 위한 명령어 재정렬 방법
    대한전자공학회 하계학술대회, 제 32권 1호, pp. 361-362, 7월, 2009년
  7. 이용호, 김태환
    파워게이팅 회로에서 복구 지연과 트랜지스터 비용 최적화 기법
    대한전자공학회 추계학술대회, 제 31권 2호, pp. 521-522, 11월, 2008년
  8. 정종윤, 김태환
    공정 변이를 고려한 상위수준 합성 기술 동향
    대한전자공학회 추계학술대회, 제 31권 2호, pp. 535-536, 11월, 2008년
  9. 임필옥, 김태환
    칩 상의 온도 상승을 억제하기 위한 상위 단계 합성
    대한전자공학회 추계학술대회, 제 31권 2호, pp. 445-446, 11월, 2008년
  10. 이병현, 김태환
    재구성 시스템에서의 온도 감지 센서 할당 문제
    대한전자공학회 추계학술대회, 제 31권 2호, pp. 491-492, 11월, 2008년
  11. 김선규, 김용주, 김태환
    FPGA 기반 시스템에서의 열 감지 센서 구현 기법
    Korea Computer Congress, 6월. 2008
  12. 현철환, 남형욱, 김용주, 김태환
    FPGA 기반 설계의 온도 센서 최적 배치 알고리즘
    Korea Computer Congress, 6월. 2008
  13. 김용환, 임경환, 김태환
    분산저장 공간을 가진 FPGA 시스템을 위한 데이터 전송 최적화
    SOC 학술대회, pp. 69-72, 5월. 2008
  14. 유예신, 김태환
    Crosstalk 제거를 위한 체계적, 저비용의 버스 인코딩 기법
    Korea Computer Congress, pp. 264-268, 10월. 2007
  15. 황동욱, 김태환
    임베디드 시스템 설계에서의 전력 소모 최소를 고려한 메모리 접근 코드 스케쥴링
    Korea Computer Congress, 2005.
  16. 김동현, 김태환
    상위단계 합성에서의 전압 할당을 고려한 자원공유
    Korea Computer Congress, 2005.
  17. 정도한, 김태환
    버스 전력 소모 최소를 위한 통합된 데이터 압축과 인코딩 기법
    Korea Computer Congress, 2005.
  18. 김동현, 김태환
    연산 회로에서의 모듈 배치를 통한 지연시간 최적화 알고리즘
    한국정보과학회 추계학술 발표회, 2004.
  19. 정도한, 김태환
    입/출력 장치의 소비전력 최적화를 위한 타스크 스케쥴링
    한국정보과학회 추계학술 발표회, 2004.
  20. 원대건, 김태환
    누설 전력 최소화를 고려한 연산 아키텍쳐 설계
    한국정보과학회 추계학술 발표회, 2004.
  21. 신건철, 김태환
    누설전류 최소화를 고려한 연산회로 합성
    SOC Conference, November 2003. (우수논문 선정)
  22. 엄준형, 이상우, 박영수, 전성익, 김태환
    스마트 카드에서의 Multiplicative Inverse 연산을 위한 효율적인 하드웨어의 구현
    _한국정보처리학회 학술대회 논문지_(A), November 2002.
  23. 엄준형, 이상우, 박영수, 전성익, 김태환
    내장형 시스템에서의 암호 연산을 위한 효율적인 역원 연산기와 나눗셈 연산기의 구현
    _한국정보과학회 컴퓨터시스템연구회 학술대회 논문지_(A), October 2002.
  24. 서재원, 김태환, 정기석
    분산된 VLIW 구조에서의 최대전력 최소화 방법
    SOC Design Conference, October 2002.
  25. 김태환
    High-level Synthesis: Its Power and Impacts in SOC Design
    SOC Design Conference, October 2002.
  26. 엄준형, 김태환
    연산회로 최적화를 위한 배선의 재배열
    한국정보과학회 춘계학술 발표회, pp. 661-663, 2002.
  27. 엄준형, 김태환
    최종 배선을 고려한 연산회로 합성
    한국정보과학회 춘계학술 발표회, pp. 664-667, 2002.
  28. 엄준형, 김태환
    WFA를 이용한 이미지 압축 알고리즘에 대한 분석
    한국정보과학회 춘계학술 발표회, pp. 727-729, 2002.
  29. 엄준형, 김태환
    저전력 회로를 위한 비트 단위의 연산 최적화
    한국정보과학회 춘계학술 발표회, pp. 16-19, 2002.
  30. 여준기, 김태환
    네트워크 플로우에 기반한 아키텍쳐 수준에서의 전력 최적화
    한국정보과학회 춘계학술 발표회, pp. 667-669, 2002.
  31. 서재원, 김태환
    상위 단계 합성에서의 스케줄링 효과를 이용한 메모리 탐색
    한국정보과학회 춘계학술 발표회, pp. 3-5, 2002.
  32. 최윤서, 김태환
    DSP 내장형 시스템 설계에서 코드 스케줄링을 이용한 주소 코드 최적화
    한국정보과학회 춘계학술 발표회, pp. 19-21, 2002.
  33. 최윤서, 김태환
    저전력 소모를 위한 상위 수준의 효과적인 바인딩 알고리즘
    한국정보과학회 춘계학술 발표회, pp. 19-21, 2002.
  34. 김태환, 엄준형, 김영태, 여준기, 홍성백
    캐리-세이브 가산기를 이용한 지연시간 최적화를 위한 연산기 합성
    _한국정보과학회 학술 대회 논문지_(A), pp. 18-20, April 2000.
  35. 엄준형, 김영태, 김태환, 여준기, 홍성백
    고속 회로를 위한 비트 단위의 연산 최적화
    _한국정보과학회 학술 대회 논문지_(A), pp. 21-23, April 2000.
  36. 김태환, 홍성백, 엄준형, 김영태, 여준기
    저전력 회로 설계를 위한 분할 버스-인버트 코딩 기법
    _한국정보과학회 학술 대회 논문지_(A), pp. 27-29, April 2000.
  37. Taewhan Kim
    Practical Issues on Behavioral Synthesis
    CAD 및 VLSI 설계 연구회 학술발표회 대회, pp.1-4, May 1999.
  38. 김태환, 엄준형
    회로 속도 최소화를 위한 캐리-세이브 가산기 모델링 및 실험
    제 6회 한국 반도체 학술 대회 (KCS), D-33, February 1999.