Deokjin Joo

Staff Researcher, Samsung Electronics, 2017.11 --

Contact

Email: djinjoo@gmail.com
Address: Bundang-gu, Seongnam-si, Gyeonggi-do, Korea

Experience

• Staff Researcher, Samsung Electronics, 2017.11 --
• PostDoc. Researcher at Professor Martin D. F. Wong's group, 2016.9 -- 2017.8

Education

• Ph.D., SNU CAD Lab., Dept. of EECS, Seoul National University, 2011.9 -- 2016.8
  • Advisor: Prof. Taewhan Kim
• M.S., SNU CAD Lab., Dept. of EECS, Seoul National University, 2009.3 -- 2011.2
  • Advisor: Prof. Taewhan Kim
• B.S., Dept. of EECS, Seoul National University, 2005.3 -- 2009.2.

Dissertation

"Clock Polarity Assignment Methodologies for Designing High-Performance and Robust Clock Trees",
Advisors: Professors Kiyoung Choi, Taewhan Kim, Ki-Seok Chung, Andrew B. Kahng, Jaeha Kim, and Dr. Woohyun Paik

Publications

Journal Articles

• Deokjin Joo and Taewhan Kim
  Clock buffer polarity assignment under useful skew constraints
  Integration, the VLSI Journal, Vol. 57, pp. 52-61, March 2017
• Juyeon Kim, Deokjin Joo and Taewhan Kim
  Optimal Utilization of Adjustable Delay Clock Buffers for Timing Correction in Designs with Multiple Power Modes
  Integration, the VLSI Journal, Vol. 52, No. 1, pp. 91-101, January 2016
• Deokjin Joo and Taewhan Kim
  A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 3, pp. 423-436, March 2014
• Kyoung-Hwan Lim, Deokjin Joo, and Taewhan Kim
  An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 3, pp. 392-405, March 2013
• Deokjin Joo, Ye-seul Kwan, Jongwoo Song, Catarina Pinho, Jody Hey and Yong-Jin Won
  Identification of Cichlid Fishes from Lake Malawi Using Computer Vision
  PLoS ONE, 8(10): e77686_, 2013
  http://www.plosone.org/article/info%3Adoi%2F10.1371%2Fjournal.pone.0077686
• Deokjin Joo, Minseok Kang, and Taewhan Kim
  Design Methodologies for Reliable Clock Networks
  Journal of Computing Science and Engineering, Vol. 6, No. 4, pp. 257-266, December 2012
• Hochang Jang, Deokjin Joo, and Taewhan Kim
  Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 1, pp. 96-109, January 2011

Proceedings

• Deokjin Joo and Taewhan Kim
  Clock Buffer Polarity Assignment Utilizing Useful Clock Skews for Power Noise Reduction
  IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2016
• Deokjin Joo and Taewhan Kim
  Managing Clock Skews in Clock Trees with Local Clock Skew Requirements Using Adjustable Delay Buffers
  International SoC Design Conference (ISOCC), pp. 137-138, November 2015
• Juyeon Kim, Deokjin Joo, and Taewhan Kim
  An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem
  IEEE/ACM Design Automation Conference (DAC), June 2013
• Younghwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sangdo Park, Deokjin Joo, and Taewhan Kim
  Clock Design Techniques Considering Circuit Reliability
  IEEE International SOC Design Conference (ISOCC), pp. 142-145, November 2011
• Deokjin Joo and Taewhan Kim
  WaveMin: A Fine-Grained Clock Buffer Polarity Assignment Combined with Buffer Sizing
  IEEE/ACM Design Automation Conference (DAC), pp. 522-527, June 2011

Patents

• Deokjin Joo and Taewhan Kim, "Adjustable Delay Buffer for Considering Slew Variation of Signal", Korean Patent No. 1013422140000, 2013-12-10.

Projects

• Global Frontier, Data syncing between Smartphones and Video Event Data Recorders (VEDR) in vehicles, funded by Korean Ministry of Education, Science, and Technology. 2015.1 -- 2015.8
• Global Frontier, Cooling methods for Video Event Data Recorders (VEDR) in vehicles, funded by Korean Ministry of Education, Science, and Technology. 2014.1 -- 2014.12
• A project with Samsung Electronics, clock tree and ADB related research. 2013
• VHDL2Verilog project, with Entasys Design Inc.,
  One of the two people who worked on the project. Managed the project schedule and did programming. 2012
• "Cooperative Control of Multiple Unmanned Aerial Vehicles for Payload Delivery", a project with Korea Agency for Defense Development,
  The lead programmer, manager of issue tracking system (Trac) and vehicle finite state machine designer. 2008.8 - 2009.12.

Teaching and Assistantships

• Teaching Assistant, EECS, SNU, Data Structures and Algorithms, 2013 fall
• Teaching Assistant, EECS, SNU, Logic Design and Concepts, 2011 winter
• Teaching Assistant EECS, SNU, Data Structures and Algorithms, 2011 fall
• Teaching Assistant, EECS, SNU, Logic Design and Concepts, 2011 summer
• Teaching Assistant, EECS, SNU, Digital Computer Concepts and Practice, 2011 spring
• Teaching Assistant, EECS, SNU, Digital Computer Concepts and Practice, 2010 spring; responsibilities: conducting practice sessions each week, grading assignments, grading exams, teaching extra materials not covered in class.
• Teaching Assistant, EECS, SNU, Logic Design and Experiments, 2010 summer; responsibilities: guiding experiment sessions twice a week, grading exams, grading term-projects.

Open Source Contributions

• https://github.com/forcecore/Keras-GAN-Animeface-Character, 148 Stars and 36 Forks as of 2020-02
• https://github.com/forcecore/pidgin-nateon
• https://github.com/OpenRA/OpenRA

Services

• Maintenance of SNUCAD Lab.'s computing resources: Workstations, the web server (http://snucad.snu.ac.kr) and the Email system (*@snucad.snu.ac.kr), 2009 -- 2016.
• SoS (Sys-admin of SoEE), EECS, SNU, Apr. 2006 -- Dec. 2008.
  • The head of the group from Aug. 2006 -- Jan. 2008.
  • Ran servers, including the ones which run http://ece.snu.ac.kr, http://eei.snu.ac.kr and http://eenet.snu.ac.kr.
  • Ran Email system (*@ee.snu.ac.kr).
  • Also maintained the computing facility, which has more than 120 PCs.

Miscellaneous

• Was a contributor of open source 'pidgin-nateon' project, which is a protocol module for Pidgin, a free, universal chat client. (The protocol lost its popularity after the introduction of smartphones)
• Wrote a machine description for GCC compiler in 2008, targeting a simple educational purpose RISC processor. This processor is coded in Verilog HDL language over the experiment sessions in 'Digital System Design and Experiments' undergraduate course. Although the course covers the design of the processor, it does not include writing a compiler. http://forcecore.tistory.com/763 (Korean).